k4d261638k Samsung Semiconductor, Inc., k4d261638k Datasheet
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k4d261638k
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k4d261638k Summary of contents
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... K4D261638K 128Mbit GDDR SDRAM Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... K4D261638K Revision History Revision Month Year 0.0 January 2006 1.0 September 2006 1.1 October 2006 1.2 November 2006 1.3 July 2007 - Target Spec - Defined target specification - Added the Current Spec - Added the IBIS Data - Added and Revised the IBIS Data - Added power up comment - Revised voltage comment of power up sequence ...
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... GENERAL DESCRIPTION FOR 2M x 16Bit x 4 Bank DDR SDRAM The K4D261638K is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized 2,097,152 words by 16 bits, fab- ricated with SAMSUNG s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high perfor- ’ ...
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... K4D261638K 4.0 PIN CONFIGURATION PIN DESCRIPTION CK,CK Differential Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe CAS Column Address Strobe WE Write Enable L(U)DQS Data Strobe L(U)DM Data Mask RFU Reserved for Future Use (Top View DDQ 4 DQ ...
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... K4D261638K 5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type *1 Input CK, CK CKE Input CS Input RAS Input CAS Input WE Input LDQS,UDQS Input/Output LDM,UDM Input Input/Output Input Input Power Supply Power Supply DDQ SSQ V Power Supply REF ...
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... K4D261638K 6.0 BLOCK DIAGRAM (2Mbit x 16I Bank) Bank Select CK,CK ADDR LCKE LRAS LCBR CK,CK CKE 16 Intput Buffer CK, CK Data Input Register Serial to parallel 2Mx16 2Mx16 2Mx16 2Mx16 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS ...
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... K4D261638K 7.0 FUNCTIONAL DESCRIPTION 7.1 Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply V before or with Apply V before or with DDQ - The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD min and the power voltage ramps are without any slope reversal 2 ...
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... K4D261638K 7.2 MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different appli- cations ...
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... K4D261638K 7.3 EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. ...
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... K4D261638K 7.4 WRITE INTERRUPTED BY A READ A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM ...
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... IH DDQ 5. V (mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate For any pin under test input of 0V < For K4D261638K-LC50, V & 2.375V to 2.7V. DD DDQ 9.2 DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted ( TA=0 to 65°C) Parameter ...
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... K4D261638K 9.3 AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to V Parameter Input High (Logic 1) Voltage; DQ Input Low (Logic 0) Voltage; DQ Clock Input Differential Voltage; CK and CK Clock Input Crossing Point Voltage; CK and CK Note : the magnitude of the difference between the input level on CK and the input level on CK. ...
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... K4D261638K 9.5 CAPACITANCE Parameter Input capacitance( CK Input capacitance ~ Input capacitance( CKE, CS, RAS,CAS Data & DQS input/output capacitance(DQ Input capacitance(DM0 ~ DM3) DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Parameter Decoupling Capacitance between V DD Decoupling Capacitance between V DDQ 1 ...
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... For normal write operation, even numbers of Din are to be written inside DRAM. 2. tRCDWR should be always greater or equal to 2tCK. AC CHARACTERISTICS (III)_Continued K4D261638K-LC40 Frequency Cas Latency 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 133MHz ( 7.5ns ) K4D261638K-LC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 133MHz ( 7.5ns ) Symbol Min tRC 52 tRFC ...
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... K4D261638K 10.0 SIMPLIFIED TIMING Simplified Timing @ BL CK, CK BA[1:0] BAa BAa A8/AP Ra ADDR Ra Ca (A0~A7 ,A9~A11) WE DQS Da0 Da1 Da2 Da3 DQ DM COM ACT_A WR_A t RCD t RAS Normal Write Burst (@ BL= BAa PRECH ACT_A /19 - 128M GDDR SDRAM 13 14 ...
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... K4D261638K IBIS : Pull up Pullup Current(mA) Voltage 100% Min 0.00 0.00 0.10 -1.00 0.20 -5.64 0.30 -10.08 0.40 -14.40 0.50 -18.40 0.60 -22.32 0.70 -26.00 0.80 -29.40 0.90 -32.52 1.00 -35.44 1.10 -37.92 1.20 -40.20 1.30 -42.08 1.40 -43.76 1.50 -45.16 1.60 -46.28 1.70 -47.24 1.80 -48.12 1.90 -48.88 2.00 -49.56 2.10 -50.20 2.20 -50.76 2.30 -51.36 2.40 -51.41 2.50 -51.63 2.60 -51.71 2.70 -51.92 0 -10 -20 -30 -40 -50 -60 -70 -80 Pullup Current(mA) 100% Max 60% Min 60% Max 0.00 0.00 -0.76 -1.16 -1.00 -6.16 -5.40 -5.92 -11.56 -9.40 -10.80 -16.68 -13.32 -15.48 -21.60 -17.00 -20.08 -26.64 -20.40 -24.40 -31.32 -23.76 -28.68 -35.96 -26.72 -32.72 -40.24 -29.48 -36.60 -44.36 -32.00 -40.36 -48.40 -34.20 -43.92 -51.92 -36.20 -47.04 -55.36 -37.80 -49.96 -58.32 -39.20 -52.60 -61.00 -40.40 -54.92 -63.40 -41.40 -57.00 -65.48 -42.28 -58.76 -67.20 -43.00 -60.24 -68.76 -43.68 -61.60 -70.08 -44.28 -62.72 -71.24 -44.84 -63.72 -72.24 -45.32 -64.60 -73.16 -45.80 -65.36 -73.96 -46.10 -66.16 -74.72 -46.31 -66.76 -75.40 -46.49 -67.40 -76.04 -46.61 -67.92 Pull up Voltage ( /19 - 128M GDDR SDRAM Pullup Current(mA) 30% Min 30% Max 0.00 0.00 0.00 -1.28 -1.24 -4.20 -4.72 -7.00 -8.08 -9.64 -11.28 -12.04 -14.40 -14.44 -17.44 -16.68 -20.32 -18.64 -23.12 -20.40 -25.72 -22.04 -28.20 -23.44 -30.52 -24.64 -32.52 -25.64 -34.40 -26.48 -36.04 -27.20 -37.48 -27.84 -38.64 -28.32 -39.72 -28.76 -40.64 -29.20 -41.40 -29.60 -42.04 -29.88 -42.64 -30.20 -43.16 -30.48 -43.68 -30.65 -44.08 -30.81 -44.52 -30.97 -44.88 -31.10 -45.24 100% Min 100% Max 60% Min 60% Max 30% Min 30% Max Rev. 1.3 July 2007 ...
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... K4D261638K IBIS : Pull down Pulldown Current(mA) Voltage 100% Min 0.00 0.00 0.10 1.24 0.20 6.72 0.30 12.00 0.40 17.16 0.50 21.84 0.60 26.16 0.70 30.32 0.80 33.92 0.90 37.00 1.00 39.68 1.10 41.76 1.20 43.32 1.30 44.48 1.40 45.36 1.50 46.00 1.60 46.44 1.70 46.88 1.80 47.20 1.90 47.56 2.00 47.88 2.10 48.12 2.20 48.36 2.30 48.60 2.40 48.80 2.50 49.04 2.60 49.24 2.70 49. Pulldown Current(mA) 100% Max 60% Min 60% Max 0.00 0.00 0.84 1.24 7.28 5.96 13.68 10.48 12.12 19.88 14.80 17.44 25.88 18.80 22.60 31.52 22.56 27.48 37.12 26.04 32.20 42.44 28.96 36.64 47.28 31.56 40.80 51.80 33.72 44.52 55.84 35.32 47.72 59.24 36.52 50.48 62.12 37.44 52.72 64.40 38.04 54.48 66.16 38.60 55.88 67.48 39.00 56.84 68.56 39.32 57.64 69.28 39.68 58.24 69.88 39.88 58.72 70.40 40.12 59.12 70.84 40.36 59.44 71.20 40.56 59.72 71.56 40.76 60.00 71.88 40.96 60.28 72.16 41.16 60.48 72.40 41.36 60.72 72.64 41.52 60.92 Pull down Voltage ( /19 - 128M GDDR SDRAM Pulldown Current(mA) 30% Min 30% Max 0.00 0.00 0.00 0.96 1.36 1.24 6.48 4.64 5.24 7.72 9.04 10.68 12.76 13.44 16.24 15.92 19.64 18.08 22.84 20.00 25.80 21.52 28.40 22.72 30.76 23.64 32.64 24.24 34.20 24.76 35.40 25.12 36.24 25.36 37.00 25.60 37.48 25.84 37.88 26.00 38.20 26.20 38.48 26.32 38.68 26.48 38.88 26.60 39.08 26.76 39.24 26.84 39.40 26.96 39.60 27.12 39.68 27.20 39.84 100% Min 100% Max 60% Min 60% Max 30% Min 30% Max Rev. 1.3 July 2007 ...
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... K4D261638K #66 #1 (1.50) (0.71) NOTE REFERENCE ASS’Y OUT QUALITY #34 #33 22.22±0.10 (10×) 0.65TYP 0.30±0.08 0.65±0.08 (10× /19 - 128M GDDR SDRAM Units : Millimeters (10×) (10×) +0.075 0.125 -0.035 0.10 MAX 0.25TYP [ ] 0.075 MAX 0×~8× Rev. 1.3 July 2007 ...