k4d261638k Samsung Semiconductor, Inc., k4d261638k Datasheet - Page 8

• Manufacturer Part Number: k4d261638k
• Description: 128mbit Gddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

7.2 MODE REGISTER SET(MRS)
K4D261638K
mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different appli-
cations. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper
operation. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with
CKE already high prior to writing into the mode register). The state of address pins A
RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in
the mode register. The mode register contents can be changed using the same command and clock cycle requirements during opera-
tion as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length
uses A
used for DLL reset. A
burst length, addressing modes and CAS latencies.
*1 : RFU(Reserved for future use)
RFU
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing
BA1
BA
should stay "0" during MRS cycle.
MRS Cycle
Command
0
1
CK, CK
0
*1
0
~ A
BA0
2
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum tRP is required to issue MRS command.
0
, addressing mode uses A
A
EMRS
n
MRS
DLL
~ A
A11
A8
0
1
0
7,
NOP
A
8
, BA
DLL Reset
RFU
A10
0
Yes
0
No
*1
and BA
Precharge
All Banks
A9
3
1
1
, CAS latency(read latency from column address) uses A
must be set to low for normal MRS operation. Refer to the table for specific codes for various
DLL
A8
CAS Latency
Test Mode
NOP
A
0
0
0
0
1
1
1
1
A
6
0
1
7
2
TM
A7
A
t
0
0
1
1
0
0
1
1
RP
5
Normal
mode
NOP
Test
A
0
1
0
1
0
1
0
1
A6
4
3
CAS Latency
- 8 /19 -
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Latency
MRS
A5
2
3
Burst Type
4
A
0
1
3
A4
t
MRD
NOP
Sequential
=2 t
Interleave
5
Burst Length
BT
A3
Type
0
CK
A
0
0
0
0
1
1
1
1
~ A
2
Command
11
Any
A
A2
0
0
1
1
0
0
1
1
and BA
1
128M GDDR SDRAM
6
4
Burst Length
~ A
A
0
1
0
1
0
1
0
1
0
6
A1
0
. A
NOP
, BA
Sequential
7
Reserve
Reserve
Reserve
Reserve
Reserve
is used for test mode. A
1
7
Rev. 1.3 July 2007
in the same cycle as CS,
A0
2
4
8
Burst Type
NOP
Address Bus
Mode Register
8
Interleave
Reserve
Reserve
Reserve
Reserve
Reserve
2
4
8
8
is