k4d261638k Samsung Semiconductor, Inc., k4d261638k Datasheet - Page 7

• Manufacturer Part Number: k4d261638k
• Description: 128mbit Gddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

7.0 FUNCTIONAL DESCRIPTION
7.1 Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
* When the operating frequency is changed, DLL reset should be required again.
K4D261638K
Command
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
*1
*
Power up & Initialization Sequence
1,2
CK,CK
7. Issue precharge command for all banks of the device.
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
stable for 200us
Inputs must be
- Apply V
- The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD min and
- Apply V
the power voltage ramps are without any slope reversal
0
ALL Banks
precharge
DD
DDQ
1
before
before
2
t
RP
or with
or with
3
EMRS
V
4
DDQ
V
2 Clock min.
REF
.
5
& V
DLL Reset
MRS
TT
6
2 Clock min.
7
ALL Banks
precharge
8
- 7 /19 -
9
tRP
10
1st Auto
Refresh
200 Clock min.
11
t
12
RFC
13
2nd Auto
Refresh
14
128M GDDR SDRAM
15
t
RFC
16
Rev. 1.3 July 2007
17
Register Set
Mode
18
2 Clock min.
19
Command
Any