mt18hts25672chy-667 Micron Semiconductor Products, mt18hts25672chy-667 Datasheet - Page 12

• Manufacturer Part Number: mt18hts25672chy-667
• Description: 2gb, 4gb X72, Dr 200-pin Ddr2 Sdram Socdimm
• Manufacturer: Micron Semiconductor Products

SMBus Slave Subaddress Decoding
Figure 3:
PDF: 09005aef8253e3ea/Source: 09005aef8253e404
HTS18C256_512x72CH.fm - Rev. B 6/07 EN
critical temperature only mode
Alarm window (MAX)
Alarm window (MIN)
EVENT# Pin Functionality
comparator mode
interrupt mode
Critical
EVENT#
EVENT#
EVENT#
The interrupt mode enables software to reset EVENT# after a critical temperature
threshold has been detected. Threshold points are set in the configuration register by the
user. This mode triggers the critical temperature limit and both the MIN and MAX of the
temperature window.
The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by
the user and only returns to the logic HIGH state when the temperature falls below the
programmed thresholds.
Critical temperature mode triggers EVENT# only when the temperature has exceeded
the programmed critical trip point. When the critical trip point has been reached, the
temperature sensor goes into comparator mode and the critical EVENT# cannot be
cleared through software.
The temperature sensor’s physical address differs from the module’s SPD device physical
addresses: 0011 for A0, A1, A2, and RW# in binary where A2, A1, and A0 are the three
slave subaddress pins and the RW# pin is the READ/WRITE flag.
If the slave base address is fixed for the SPD and temperature sensor, then the pins set
the subaddress bits of the slave address, enabling the devices to be located anywhere
within the eight slave address locations. For example, they could be set from 30h to 3Eh.
Temperature
Clears event
2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM
12
Hysteresis affects
these trip points
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Temperature Sensor
©2006 Micron Technology, Inc. All rights reserved.
Time