mt18hts25672chy-667 Micron Semiconductor Products, mt18hts25672chy-667 Datasheet - Page 4

• Manufacturer Part Number: mt18hts25672chy-667
• Description: 2gb, 4gb X72, Dr 200-pin Ddr2 Sdram Socdimm
• Manufacturer: Micron Semiconductor Products

Table 6:
PDF: 09005aef8253e3ea/Source: 09005aef8253e404
HTS18C256_512x72CH.fm - Rev. B 6/07 EN
RAS#, CAS#, WE#
DQS0#–DQS8#
DQS0–DQS8,
ODT0, ODT1
CKE0, CKE1
DQ0–DQ63
DM0–DM8
CK0, CK0#
BA0–BA2
SA0–SA1
CB0–CB7
Symbol
S0#, S1#
A0–A13
A0–A14
EVENT#
V
(2GB)
(4GB)
SDA
V
V
DDSPD
SCL
V
NC
REF
DD
SS
Pin Descriptions
Output
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
–
Description
On-die termination: ODT (registered HIGH) enables termination resistance
internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the
following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled
via the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW)
deactivates clocking circuitry on the DDR2 SDRAM.
Chip select: S# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when S# is registered HIGH. S#
provides for external rank selection on systems with multiple ranks. S# is considered
part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Bank address inputs: BA0–BA2 define to which device bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. BA0–BA2 define which mode
register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE
command.
Address inputs: Provide the row address for ACTIVE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one device
bank (A10 LOW, device bank selected by BA0–BA2) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a LOAD MODE command.
Input data mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is
sampled on both edges of DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.
Serial clock: SCL is used to synchronize the presence-detect and temperature
sensor data transfer to and from the module.
Serial address inputs: These pins are used to configure the presence-detect and
temperature sensor devices.
Data input/output: Bidirectional data bus.
Check bits.
Data strobe: Output with read data, input with write data for source synchronous
operation. Edge-aligned with read data, center-aligned with write data. DQS# is
only used when differential data strobe mode is enabled via the LOAD MODE
command.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and
out of the presence-detect and temperature sensor portion of the module.
Temperature sensor alarm output.
Power supply: +1.8V ±0.1V.
SSTL_18 reference voltage. V
Ground.
Serial EEPROM and temperature sensor positive power supply:
+3.0V to +3.6V.
No connect: These pins should be left unconnected.
2GB, 4GB (x72, DR) 200-Pin DDR2 SDRAM SOCDIMM
4
DD
/2.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
©2006 Micron Technology, Inc. All rights reserved.