mt9v011p11st Micron Semiconductor Products, mt9v011p11st Datasheet
mt9v011p11st
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mt9v011p11st Summary of contents
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... PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONL Y AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONL Y WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DAT A SHEET SPECIFICATIONS. 1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR MT9V011 Micron Part Number: MT9V011P11ST T able 1: Key Performance Parameters PARAMETER Optical Format ...
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T able of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of T ables Table 1: Key Performance Parameters ...
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Figure 2: Typical Configuration (Connection) 1.5KΩ Two-wire serial bus 09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN 1/4-INCH VGA CMOS ACTIVE-PIXEL Figure 1: Block Diagram Control Register APS Array 668H x 496V Timing and Control ADC V DD 1KΩ RESET_BAR 10µF ...
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Figure 3: Pin Out Diagram - 28-Pin PLCC VAAPIX SCAN_EN RESET_BAR ST ANDBY T able 2: Pin Descriptions PIN NUMBER NAME VAAPIX GND 11,13 A GND 4 CLK_IN 19 OE_BAR 16 ...
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T able 2: Pin Descriptions (continued) PIN NUMBER NAME OUT OUT OUT 6 FRAME_VALID 7 LINE_VALID 5 PIXCLK 09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN 1/4-INCH VGA ...
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Pixel Data Format Pixel Array Structure The MT9V011’ s pixel array is 668 columns by 496 rows. The first 18 columns and the first 6 rows of pixels are optically black and can be used to monitor the black level. ...
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Output Data Timing The data output of the MT9V011 is synchronized with the PIX CLK output. When LINE_V ALID is HIGH, one 10-bit pixel datum is output every PIX CLK period. Figure 7: Timing Example of Pixel Data LINE_VALID PIXCLK ...
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Frame Timing Formulas T able 3: Frame Time PARAMETER NAME A Active Data Time P Frame Start/End Blanking 6 x (Reg0x0A + 2) Q Horizontal Blanking A+Q Row Time V Vertical Blanking Frame Valid Time ...
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Serial Bus Description Registers are written to and read from the MT9V 011 through the two-wire serial interface bus. The sensor is a serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial ...
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No-Acknowledge Bit The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence. 09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN ...
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T wo-Wire Serial Interface Sample Read and Write Sequences 16-Bit Write Sequence A typical write sequence for writing 16 bits to a reg- ister is shown in Figure 9. A start bit given by the mas- ter, followed by the ...
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Eight-Bit Write Sequence To be able to write one byte at a time to the register a special register address is added. The eight-bit write is done by first writing the upper eight bits to the desired register and then ...
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Registers Register Map T able 6: Register Map REGISTER # (HEX) DESCRIPTION 0x00/0xFF Chip Version 0x01 Row Start 0x02 Column Start 0x03 Window Height 0x04 Window Width 0x05 Horizontal Blanking 0x06 Vertical Blanking 0x07 Output Control 0x09 Shutter Width 0x0A ...
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T able 6: Register Map (continued) REGISTER # (HEX) DESCRIPTION 0x5C Reserved 0x5D Reserved 0x5E Reserved 0x5F Reserved 0x60 Reserved 0x61 Reserved 0x62 Reserved 0x63 Reserved 0x64 Reserved 0x65 Reserved 0xF1 Chip Enable 0xF7 Reserved 0xF8 Reserved 0xF9 Reserved 0xFA ...
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Register Descriptions T able 7: Register Description REGISTER BIT Chip Version 0x00 / 0xFF 0-15 This register is read-only and gives the chip identificat ion number: 0x8232. Window Control These registers control the size of the window. 0x01 0-8 First ...
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T able 7: Register Description (continued) REGISTER BIT Pixel Integration Control These registers (along with the Window S ize and Blanking registers) control the integration time for the pixels. 0x09 0-11 Number of rows of integration, default = 0x01FC (508). ...
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T able 7: Register Description (continued) REGISTER BIT Read Mode This register is used to control many aspects readout of the sensor. 0x20 0 Show bad frames output all frames (including bad frames ...
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T able 7: Register Description (continued) REGISTER BIT 0x35 GlobalGain — When read, it will return the value stored in Reg0x2B. 0-6 Initial Gain = bit s (6-0) x 0.03125 Analog Gain = (Bit ...
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Feature Description Window Control Reg0x01 Row Start, Reg0x02 Column Start, Reg0x03 Window Height (row size), and Reg0x04 Window Width (column size) These registers control the size and starting coordi- nates of the window. By changing these registers, any image format ...
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Digital Zoom Reg0x1E Digital Zoom/True decimation In zoom mode, the pixel data rate is slowed down by a factor of either and either additional blank rows are added between each output row. This is ...
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Figure 15: Readout of 6 Pixels in Normal and Column Mirror Output Mode LINE_VALID Normal readout D Reverse readout D Row Mirror Image By setting bits 15 and 7 of Reg0x20 the readout order of the rows will be reversed, ...
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Recommdended Gain Settings The gains for green1, blue, red, and green2 pixels are set by registers Reg0x2B, Reg0x2C, Reg0x2D, and Reg0x2D, respectively. Gain can also be set globally by Reg0x35. The analog gain is set by bits[8:0] of the cor- ...
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Electrical Specifications T able 10: DC Electrical Characteristics (V = 2.8 ±0.25V Ambient = 25 PWR A SYMBOL DEFINITION V Input High Voltage IH V Input Low Voltage IL I Input Leakage Current IN V Output High Volt ...
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T able 11: AC Electrical Characteristics (V = 2.8 ±0.25V Ambient = SYMBOL DEFINITION f _ Input Clock Frequency CLK IN Clock Duty Cycle t Input Clock Rise Time R t Input Clock Fall Time ...
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Propagation Delays for PIXCLK and Data Out Signals The typical output delay, relative to the master clock edge, is 7.5 ns. Note that the data outputs change on the falling edge of the master clock, with the pixel clock rising ...
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Figure 21: Data Output Timing Diagram t FVSETUP PIXCLK t LVSETUP FRAME_VALID t FTOL LINE_VALID D (9:0) OUT t outF t outR PIX CLK = max. 27 MHz t FVSETUP = / setup time for FRAME_V A LID before rising ...
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Tw o-Wire Serial Bus Timing The two-wire serial bus operation requires certain minimum master clock cycles between transitions. These are specified in the following diagrams in mas- ter clock cycles. Figure 22: Serial Host Interface Start Condition Timing 5 SCLK ...
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MT9V011_external_DS_2.fm - Rev. A 8/04 EN 1/4-INCH VGA CMOS ACTIVE-PIXEL Figure 28: Spectral Response Relative Spectral Response 550 650 750 Wavelength (nm) Micron Technology, Inc., reserves the right to change ...
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NOTE: Image center = package center. Not to scale. Chip Center NOTE: Not to scale. 09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN 1/4-INCH VGA CMOS ACTIVE-PIXEL Figure 29: Die Placement 11.43mm Package center Pixel Array Pixel (0,0) Image center ...
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Figure 31: 28-Pin PLCC Package Outline Drawing 1.70 ±0.10 2.35 ±0.15 SEATING PLANE SECTION A–A 7.62 1.27 TYP 28 1 27X 1.27 29X R0.225 7. 1.905 ±0.100 11.43 ±0.10 Data Sheet Designation Preliminary: This data sheet contains initial ...
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Revision History Rev A, Preliminary...........................................................................................................................................................4/04 • Initial Release of document 09005aef80c6407f MT9V011_external_DS_2.fm - Rev. A 8/04 EN 1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Micron Technology, Inc., reserves the right to change products or specifications without notice. 33 Preliminary ©2004 ...