mt9v011p11st Micron Semiconductor Products, mt9v011p11st Datasheet - Page 23

• Manufacturer Part Number: mt9v011p11st
• Description: 1/4-inch Vga Cmos Active-pixel Digital Image Sensor
• Manufacturer: Micron Semiconductor Products

Row Mirror Image
of the rows will be reversed, as shown in Figure 16.
Column and Row Skip
set will be read out, as shown in Figure 17. The row
skip works in the same way and will only read out two
Line Valid
nal can get three different output formats. The formats
are shown in Figure 18 when reading out four rows
09005aef80c6407f
MT9V011_external_DS_2.fm - Rev. A 8/04 EN
By setting bits 15 and 7 of Reg0x20 the readout order
By setting bit 3 of Reg0x20 only half of the columns
By setting bit 9 and 10 of Reg0x20 the line valid sig-
Figure 15: Readout of 6 Pixels in Normal and Column Mirror Output Mode
Figure 17: Readout of 8 Pixels in Normal and Column Skip Output Mode
Figure 16: Readout of 6 Rows in Normal and Row Mirror Output Mode
Column skip readout
LINE_V ALID
Normal readout
DOUT9-DOUT0
LINE_V ALID
DOUT9-DOUT0
Reverse readout
Normal readout
Reverse readout
DOUT9-DOUT0
Normal readout
DOUT9-DOUT0
FRAME_VALID
Figure 18: Different Line Valid Formats
D
D
LINE_VALID
OUT9
OUT9
FRAME_VALID
FRAME_VALID
FRAME_VALID
Continuously
LINE_VALID
LINE_VALID
LINE_VALID
-D
-D
Default
OUT0
OUT0
XOR
(9:0)
(9:0)
G0
G0
Row 6 Row5 Row4 Row3
Row0
(9:0)
(9:0)
(9:0)
(9:0)
R0
R0
(9:0)
(9:0)
G3
G0
Row1
(9:0)
(9:0)
23
(9:0)
(9:0)
G1
G2
1/4-INCH VGA CMOS ACTIVE-PIXEL
(9:0)
(9:0)
R0
R2
Row2
(9:0)
out of four rows. For both row and column skip the
number of rows/columns read out will be half of what
is set in Reg0x03 and Reg0x04.
and two vertical blanking rows. In the last format the
line valid signal is the XOR between the continuously
line valid signal and the frame valid signal.
(9:0)
(9:0)
(9:0)
R1
R2
(9:0)
(9:0)
Row3
G2
(9:0)
G1
(9:0)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(9:0)
G2
Row2 Row1
Row4
(9:0)
(9:0)
(9:0)
(9:0)
R1
R1
(9:0)
R2
DIGITAL IMAGE SENSOR
Row5
(9:0)
(9:0)
(9:0)
(9:0)
G2
G1
(9:0)
G3
(9:0)
(9:0)
R0
R2
(9:0)
R3
©2004 Micron Technology, Inc.
Preliminary