mt9v011p11st Micron Semiconductor Products, mt9v011p11st Datasheet - Page 10

• Manufacturer Part Number: mt9v011p11st
• Description: 1/4-inch Vga Cmos Active-pixel Digital Image Sensor
• Manufacturer: Micron Semiconductor Products

Frame Timing Formulas
T able 3:
constant value in default mode, when 8 dark columns
are read out through Reg0x30. The constant follows
the dark columns read out as shown in Table 4.
T able 4:
tions assume that the number of integration rows (bits
11 through 0 of Reg0x09) is less than the number of
active plus blanking rows (Reg0x03 + 1 + Reg0x06 + 1).
T able 5:
09005aef80c6407f
MT9V011_external_DS_2.fm - Rev. A 8/04 EN
PARAMETER
PARAMETER
A
P
Q
A+Q
V
N
F
V’
F’
rows
The constant 113 in the formulas in Table 3 is the
The vertical blanking and total frame time equa-
REG 0X30, BIT 1:0
x (A + Q) Frame Valid Time
1x
01
00
Frame Time
Constant Value
Frame Time - Master Clock
Total Frame Time (long
Vertical Blanking (long
integration time)
integration time)
Active Data Time
Frame Start/End Blanking 6 x (Reg0x0A + 2)
Horizontal Blanking
Row Time
Vertical Blanking
Total Frame Time
NAME
NAME
CONSTANT
121
113
107
(Reg0x03 + 1) x (A + Q) - (Q - 2 x P)
(Reg0x03 + 1 + Reg0x06 + 1) x (A + Q)
(Reg0x04 + 1) x (Reg0x0A + 2)
(113 + Reg0x05) x (Reg0x0A + 2)
(minimum Reg0x05 value = 9)
(Reg0x04 + 1 + 113 + Reg0x05) x (Reg0x0A + 2) 884 pixel clocks
(Reg0x06 + 1) x (A + Q) + (Q - 2 x P)
(Reg0x09 - Reg0x03) x (A + Q) + (Q - 2 x P)
(Reg0x09 + 1) x (A + Q)
For 16 columns
For 8 columns
For no dark columns read, no row-wise noise correction applied
EQUATION (MASTER CLOCK)
10
EQUATION
1/4-INCH VGA CMOS ACTIVE-PIXEL
and master clock cycles (please refer to Figure 7). The
recommended master clock frequency is 27 MHz.
If this is not the case, the number of integration rows
must be used instead to determine the frame time, as
shown in Table 5.
Sensor timing is shown above in terms of pixel clock
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DIGITAL IMAGE SENSOR
DEFAULT TIMING AT 27 MHZ
640 pixel clocks
= 1280 master
= 47.4µs
6 pixel clocks
= 12 master
= 0.44µs
244 pixel clocks
= 488 master
= 18.07µs
= 1,768 mast er
= 65.48µs
25,868 pixel clocks
= 51,736 master
= 1.92ms
424,088 pixel clocks
= 848,176 master
= 31.41ms
449,956 pixel clocks
= 899,912 master
= 33.33ms
25,868 pixel clocks
= 51,736 master
= 1.92 ms
449,956 pixel clocks
= 899,912 master
= 33.33ms
DEFAULT TIMING
©2004 Micron Technology, Inc.
Preliminary