mt9v011p11st Micron Semiconductor Products, mt9v011p11st Datasheet - Page 22

• Manufacturer Part Number: mt9v011p11st
• Description: 1/4-inch Vga Cmos Active-pixel Digital Image Sensor
• Manufacturer: Micron Semiconductor Products

Digital Zoom
a factor of either 2 or 4, and either 1 or 3 additional
blank rows are added between each output row. This is
designed to give the controller logic time to repeat
data to fill in a window that is either 2 or 4 times larger
with repeated data.
True Decimation mode
sors without color filtering. There are three modes
with different amount of decimation. In decimate 2x
every other column and row are skipped. In decimate
Read Mode
Column Mirror image
of the columns will be reversed, as shown in Figure 15.
09005aef80c6407f
MT9V011_external_DS_2.fm - Rev. A 8/04 EN
Reg0x1E Digital Zoom/True decimation
In zoom mode, the pixel data rate is slowed down by
Reg0x1E Digital Zoom/True decimation
True decimation mode is intended for use in sen-
By setting bits 14 and 5 of Reg0x20 the readout order
Figure 14: Readout of 8 Pixels in Normal and 2x Decimation Output Mode
Figure 13: Readout of 4 Pixels in Normal and Zoom 2x Output Mode
Decimate 2X readout
Normal readout
Zoom 2X readout
Normal readout
LINE_VALID
D
LINE_VALID
D
OUT9-
D
OUT9
D
LINE_VALID
LINE_VALID
OUT9
OUT9
-D
D
PIXCLK
PIXCLK
-D
-D
OUT0
OUT0
OUT0
OUT0
(9:0)
(9:0)
(9:0)
G0
P0
P0
(9:0)
G0
(9:0)
R0
(9:0)
(9:0)
P1
P2
(9:0)
G1
22
(9:0)
R0
1/4-INCH VGA CMOS ACTIVE-PIXEL
(9:0)
(9:0)
P2
P4
(9:0)
R1
tion, and the output data for each pixel is valid for
either 2 or 4 pixel clocks. In zoom by 2 mode, every row
is followed by a blank row (with its own line valid, but
all data bits = 0) of equal time. In zoom by 4 mode,
every row is followed by three blank rows. The combi-
nation of this register and an appropriate change to
the window sizing registers allows the user to zoom to
a region of interest without affecting the frame rate.
4x three rows/ columns will be skipped for every row/
column read out, and in decimate 8x seven rows/ col-
umns will be skipped for every row/column read out.
Decimate 2x is shown in Figure 14. In decimation
mode the global gain register should be used to set the
gain.
The pixel clock speed is not affected by this opera-
(9:0)
(9:0)
P3
P6
(9:0)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
G1
(9:0)
P4
(9:0)
R1
DIGITAL IMAGE SENSOR
(9:0)
P5
(9:0)
P6
(9:0)
P7
©2004 Micron Technology, Inc.
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