k4r881869m Samsung Semiconductor, Inc., k4r881869m Datasheet - Page 19

• Manufacturer Part Number: k4r881869m
• Description: 288mbit Rdram 512k X 18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

K4R881869M
Figure 12 shows examples of the PRER-to-PRER (RR13,
RR14) and PRER-to-ACT (RR9, RR10) command spacings
from Table 10. The RR15 and RR16 cases (PRER-to-PRER
to same or adjacent banks) are not shown, but are similar to
RR14. In general, the commands in ROW packets may be
Row and Column Cycle Description
Activate: A row cycle begins with the activate (ACT) opera-
tion. The activation process is destructive; the act of sensing
the value of a bit in a bank’s storage cell transfers the bit to
the sense amp, but leaves the original bit in the storage cell
with an incorrect value.
Restore: Because the activation process is destructive, a
hidden operation called restore is automatically performed.
The restore operation rewrites the bits in the sense amp back
into the storage cells of the activated row of the bank.
Read/Write: While the restore operation takes place, the
sense amp may be read (RD) and written (WR) using
column operations. If new data is written into the sense amp,
it is automatically forwarded to the storage cells of the bank
so the data in the activated row and the data in the sense amp
remain identical.
Precharge: When both the restore operation and the column
operations are completed, the sense amp and bank are
precharged (PRE). This leaves them in the proper state to
begin another activate operation.
Intervals: The activate operation requires the interval
t
the interval t
RCD,MIN
CTM/CFM
COL4
DQA8..0
DQB8..0
ROW2
..COL0
..ROW0
to complete. The hidden restore operation requires
RAS,MIN
t
T
PACKET
0
PRER a0
T
1
T
2
- t
T
3
RCD,MIN
T
PRER b0
4
T
5
T
6
T
7
to complete. Column read
T
8
T
9
T
10
T
11
T
12
PRER a0
T
Figure 12: Row Packet Examples
13
T
14
T
15
T
16
T
17
T
18
T
t
19
Page 17
PP
T
20
PRER c0
Different Device
Different Device
T
21
Same Device
Same Device
Same Device
Same Device
spaced an interval t
the same or adjacent banks or unless they are a similar
command type (both PRER or both ACT) directed to the
same device.
and write operations are also performed during the t
- t
tions are performed, this interval must be increased). The
precharge operation requires the interval t
complete.
Adjacent Banks: An RDRAM with a “s” designation
(512Kx32sx18) indicates it contains “split banks”. This
means the sense amps are shared between two adjacent
banks. The only exception is that sense amp 0, 15, 30, and
31 are not shared. When a row in a bank is activated, the two
adjacent sense amps are connected to (associated with) that
bank and are not available for use by the two adjacent banks.
These two adjacent banks must remain precharged while the
selected bank goes through its activate, restore, read/write,
and precharge operations.
For example (referring to the block diagram of Figure 2), if
bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will
both be loaded with one of the 512 rows (with 1024 bytes
loaded into each sense amp from the 2Kbyte row - 512 bytes
to the DQA side and 512 bytes to the DQB side). While this
row from bank 5 is being accessed, no rows may be accessed
in banks 4 or 6 because of the sense amp sharing.
T
22
RCD,MIN
T
23
T
24
T
25
T
26
T
interval (if more than about four column opera-
27
t
T
PACKET
28
PRER a0
Non-adjacent Bank
Non-adjacent Bank
T
29
Adjacent Bank
T
30
Same Bank
PACKET
Any Bank
Any Bank
T
31
T
32
ACT b0
T
33
T
apart unless they are directed to
34
T
35
Preliminary
Direct RDRAM
Rev. 0.9 Jan. 2000
T
36
T
RR13
RR14
RR15
RR16
RR10
37
RR9
T
38
T
39
t
T
PACKET
40
PRER a0
RP,MIN
c0 = {Da,Ba+1Rc}
b0 = {Db,Bb,Rb}
b0 = {Db,Bb,Rb}
T
a0 = {Da,Ba,Ra}
c0 = {Da,Bc,Rc}
c0 = {Da,Ba,Rc}
c0 = {Da,Bc,Rc}
41
T
42
T
43
to
T
44
ACT c0
T
RAS,MIN
45
T
46
T
47
™