emc646sp16ak Emlsi Inc., emc646sp16ak Datasheet - Page 10

• Manufacturer Part Number: emc646sp16ak
• Description: 4mx16 Bit Cellularram
• Manufacturer: Emlsi Inc.

Bus Operating Modes
64Mb CellularRAM products incorporate a burst mode interface found on Flash products targeting low-power, wireless applications.
This bus interface supports asynchronous, page mode, and burst mode read and write transfers. The specific interface supported is
defined by the value loaded into the BCR. Page mode is controlled by the refresh configuration register (RCR[7]).
Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode.This mode uses the industry- standard SRAM control bus (CE#,
OE#, WE#, and LB#/UB#). READ operations (Figure 3) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE#
HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations (Figure 4) occur when
CE#, WE#, and LB#/UB# are driven LOW. During asychronous WRITE operations, the OE# level is a “Don’t care”, and WE# will over-
ride OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asychronous opera-
tions (page mode disabled) can either use the ADV# input to latch the address, or ADV# can be driven LOW during the entire READ/
WRITE operation.
During asychronous operation, the CLK input must be held static LOW. WAIT will be driven while the device is enabled and its state
should be ignored. WE# LOW time must be limited to t
Figure 3: READ Operation (ADV# LOW)
Note: ADV# must remain Low for PAGE MODE operation.
LB#/UB#
Address
DATA
WE#
OE#
CE#
CEM
t
RC
Address Valid
= READ Cycle Time
10
Data Valid
Don’t Care
EMC646SP16AK
4Mx16 CellularRAM