emc646sp16ak Emlsi Inc., emc646sp16ak Datasheet - Page 18
emc646sp16ak
Manufacturer Part Number
emc646sp16ak
Description
4mx16 Bit Cellularram
Manufacturer
Emlsi Inc.
Datasheet
1.EMC646SP16AK.pdf
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Figure 11: Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation
Note:
1. Non-default BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation: Latency
2. A[19:18] = 00b to load RCR, and 10b to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored; additional WAIT cycles caused by refresh
code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay.
collisions require a corresponding number of additional CE# LOW cycles.
(except A[19:18])
A[19:18]
LB#/UB#
DQ[15:0]
A[21:0]
ADV#
WAIT
WE#
CRE
OE#
CLK
CE#
2
Latch control register value
High-Z
t
t
CSP
t
t
SP
t
t
OPCODE
CEW
SP
SP
SP
t
t
t
t
HD
HD
HD
HD
Latch control register address
Note 3
18
t
High-Z
CBPH
Address
Address
EMC646SP16AK
4Mx16 CellularRAM
Don’t Care
Data
Valid
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