emc646sp16ak Emlsi Inc., emc646sp16ak Datasheet - Page 57
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emc646sp16ak
Manufacturer Part Number
emc646sp16ak
Description
4mx16 Bit Cellularram
Manufacturer
Emlsi Inc.
Datasheet
1.EMC646SP16AK.pdf
(64 pages)
- Current page: 57 of 64
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Figure 46. Burst WRITE Interrupted by Burst WRITE or READ - Fixed Latency Mode
Note:
1. Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in fixed latency mode: Fixed latency; latency code two (three
2. Burst interrupt shown on first allowable clock (i.e., after first data word written).
3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than t
clocks); WAIT active LOW; WAIT asserted during delay.
DQ[15:0] IN
2nd Cycle WRITE
2nd Cycle WRITE
2nd Cycle WRITE
LB#/UB#
A[21:0]
ADV#
WAIT
WE#
CLK
OE#
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
IH
IL
IH
IL
IH
IL
High-Z
DQ[15:0] OUT
t
t
Address
SP
t
t
2nd Cycle READ
SP
2nd Cycle READ
2nd Cycle READ
CSP
SP
Valid
LB#/UB#
t
HD
t
t
High-Z
HD
HD
OE#
t
AVH
V
V
V
V
V
V
IH
IL
IH
IL
OH
OL
t
CLK
t
t
SP
SP
D0
t
t
t
HD
SP
HD
t
CEW
t
t
SP
t
SP
Address
SP
Valid
t
t
t
HD
HD
t
HD
KHTL
V
V
OH
OL
WRITE Burst interrupted with new WRITE or READ. See Note 2.
57
t
High-Z
CEM
(Note 3)
t
ACLK
t
BOE
CEM
Output
t
Valid
SP
.
D0
t
HD
t
KOH
Output
Valid
D1
Output
Valid
D2
Don’t Care
EMC646SP16AK
Output
Valid
D3
4Mx16 CellularRAM
t
t
HD
HD
t
OHZ
High-Z
Undefined
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