k4h281638l Samsung Semiconductor, Inc., k4h281638l Datasheet
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... K4H281638L 128Mb L-die DDR SDRAM Specification with Lead-Free and Halogen-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER- WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL- OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... K4H281638L Table of Contents 1.0 Key Features ...............................................................................................................................4 2.0 Ordering Information ..................................................................................................................4 3.0 Operating Frequencies ...............................................................................................................4 4.0 Pin / Ball Description ..................................................................................................................5 5.0 Package Physical Dimension ....................................................................................................6 6.0 Block Diagram (2Mb x 16 I/O x4 Banks) ....................................................................................7 7.0 FUNCTIONAL DESCRIPTION ......................................................................................................8 7.1 Power-up & Initialization Sequence 7.2 Mode Register Definition 7.3 Extended Mode Register Set(EMRS) 8.0 Input/Output Function Description .........................................................................................12 9.0 Command Truth Table ..............................................................................................................13 10.0 General Description ................................................................................................................14 11 ...
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... K4H281638L Revision History Revision Month Year 1.0 September 2008 1.1 October 2008 - Release rev.1.0 SPEC - Corrected max tCK complying JEDEC - Changed tCK max of 400/333Mbps to 10ns from 12ns - Corrected IDD1 current measurement condition DDR SDRAM History Rev. 1.1 October 2008 ...
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... Maximum burst refresh cycle : 8 • 66pin TSOP II Lead-Free and Halogen-Free • RoHS compliant 2.0 Ordering Information Part No. K4H281638L-LCCD K4H281638L-LCCC K4H281638L-LCB3 3.0 Operating Frequencies CD(DDR500@CL=3) Speed @CL2 Speed @CL2.5 Speed @CL3 CL-tRCD-tRP package Org. Max Freq. CD(DDR500@CL=3) ...
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... K4H281638L 4.0 Pin / Ball Description 66pin TSOP - II LDQS AP/A Organization DM is internally loaded to match DQ and DQS identically. 8Mb DDQ SSQ DDQ 66Pin TSOPII (400mil x 875mil (0.65mm Pin Pitch) ...
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... K4H281638L 5.0 Package Physical Dimension #66 #1 (1.50) 0.65TYP (0.71) [0.65 0.08] ± NOTE REFERENCE Detail ASS’Y OUT QUALITY #34 #33 22.22 0.10 ± (10°) (10°) Detail A Detail B Detail B 0.25 ± 0.08 0.30 ± 0.08 66Pin TSOP(II) Package Dimension DDR SDRAM +0.075 0.125 - 0.035 0.10 MAX [ [ 0.075 MAX Rev. 1.1 October 2008 Unit : mm 0 ...
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... K4H281638L 6.0 Block Diagram (2Mb x 16 I/O x4 Banks) Bank Select CK, CK ADD LCKE LRAS LCBR CK, CK CKE x4/8/16 CK, CK Data Input Register Serial to parallel x8/16/32 1Mx32 1Mx32 1Mx32 1Mx32 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS ...
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... K4H281638L 7.0 FUNCTIONAL DESCRIPTION 7.1 Power-up & Initialization Sequence DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. No power sequencing is specified during power up and power down given the following • V and V are driven from a single power converter output, AND ...
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... K4H281638L 7.2 Mode Register Definition Mode Register Set(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different appli- cations ...
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... K4H281638L Burst Starting Address(A2, Length Mode Register Set Precharge Command All Banks MRS can be issued only at all bank precharge state Minimum tRP is required to issue MRS command. Burst Address Ordering for Burst Length Sequential Mode A1, A0) xx0 0, 1 xx1 ...
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... K4H281638L 7.3 Extended Mode Register Set(EMRS) The extended mode register stores the data for enabling or disabling DLL, and selecting output driver size. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. ...
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... K4H281638L 8.0 Input/Output Function Description SYMBOL TYPE CK, CK Input CKE Input CS Input RAS, CAS, WE Input LDM,(UDM) Input BA0, BA1 Input 11] Input DQ I/O LDQS,(U)DQS I Supply DDQ V Supply SSQ V Supply DD V Supply SS V Input REF Clock : CK and CK are differential clock inputs. All address and control input signals are sam- pled on the positive edge of CK and negative edge of CK ...
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... K4H281638L 9.0 Command Truth Table COMMAND Register Extended MRS Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address ...
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... Banks Double Data Rate SDRAM 10.0 General Description The K4H281638L is 134,217,728 bits of double data rate synchronous DRAM organized as 4x 2,097,152 words by 16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 500Mb/s per pin ...
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... K4H281638L 13.0 DDR SDRAM Spec Items & Test Conditions Operating current - One bank Active-Precharge; tRC=tRCmin; tCK= 6ns for DDR333, 5ns for DDR400, 4ns for DDR500; DQ,DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. ...
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... K4H281638L 15.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A IDD1 : Operating current: One bank operation 1. Typical Case 2.5V, T=25°C DD Worst Case : V = 2.7V, T= 10° Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle ...
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... K4H281638L 16.0 DDR SDRAM IDD spec table Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal IDD7A 8Mx16 (K4H281638L) CD(DDR500@CL=3) CC(DDR400@CL=3) 120 130 200 200 200 3 300 DDR SDRAM (V DD B3(DDR333@CL=2.5) 110 100 120 120 ...
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... K4H281638L 17.0 AC Operating Conditions Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs I/O Reference Voltage Note : the magnitude of the difference between the input level on CK and the input level on CK. ...
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... K4H281638L 19.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and V The area between the undershoot signal and GND must be less than or equal to ...
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... K4H281638L 20.0 AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Clock cycle time CL=2.5 CL=3.0 Clock high level width ...
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... K4H281638L 21.0 System Characteristics for DDR SDRAM The following specification parameters are required in systems using DDR400 and DDR333 devices to ensure proper system perfor- mance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM ...
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... K4H281638L 22.0 Component Notes 1. All voltages referenced Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester ...
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... K4H281638L Component Notes 17. For CK & CK slew rate ≥ 1.0 V/ns 18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 19. Slew Rate is measured between V 20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH) ...
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... K4H281638L 23.0 System Notes a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2. Output Figure 2 : Pullup slew rate test load b. Pulldown slew rate is measured under the test conditions shown in Figure 3. Output Figure 3 : Pulldown slew rate test load c. Pullup slew rate is measured between (V ...
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... K4H281638L 24.0 IBIS : I/V Characteristics for Input and Output Buffers DDR SDRAM Output Driver V-I Characteristics DDR SDRAM Output driver characteristics are defined for full and half strength operation as selected by the EMRS bit A1. Figures 4, 5 and 6 show the driver characteristics graphically, and tables 8, 9 and 10 show the same data in tabular format suitable for input into simulation tools ...
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... K4H281638L Pulldown Current (mA) Typical Typical Voltage (V) Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 0.6 34.6 39.1 0.7 39.4 44.2 0.8 43.7 49.8 0.9 47.5 55.2 1.0 51.3 60.3 1.1 54.1 65.2 1.2 56.2 69.9 1.3 57.9 74.2 1.4 59.3 78.4 1.5 60.1 82.3 1.6 60.5 85.9 1.7 61.0 89.1 1.8 61.5 92.2 1.9 62.0 95.3 2.0 62.5 97.2 2.1 62.9 99.1 2.2 63.3 100.9 2.3 63.8 101.9 2.4 64.1 102.8 2.5 64.6 103.8 2.6 64.8 104.6 2.7 65.0 105.4 Minimum Maximum 4.6 9.6 9.2 18.2 13.8 26.0 18.4 33.9 23.0 41.8 27.7 49.4 32.2 56.8 36.8 63.2 39.6 69.9 42.6 76.3 44.8 82.5 46.2 88.3 47.1 93.8 47.4 99.1 47.7 103.8 48.0 108.4 48.4 112.1 48.9 115.9 49.1 119.6 49.4 123.3 49.6 126.5 49.8 129.5 49.9 132.4 50.0 135.0 50.2 137.3 50.4 139.2 50.5 140.8 Table 8. Full Strength Driver Characteristics DDR SDRAM pullup Current (mA) Typical Typical ...
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... K4H281638L 0.0 Pulldown Characteristics for Weak Output Driver 0.0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 Pullup Characteristics for Weak Output Driver Figure 5. I/V characteristics for input/output buffers:Pulldown(above) and pullup(below) 1.0 2.0 1.0 2 DDR SDRAM Maximum Typical High Typical Low Minimum Vout(V) Minumum ...
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... K4H281638L Pulldown Current (mA) Typical Typical Voltage (V) Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 0.6 19.6 22.1 0.7 22.3 25.0 0.8 24.7 28.2 0.9 26.9 31.3 1.0 29.0 34.1 1.1 30.6 36.9 1.2 31.8 39.5 1.3 32.8 42.0 1.4 33.5 44.4 1.5 34.0 46.6 1.6 34.3 48.6 1.7 34.5 50.5 1.8 34.8 52.2 1.9 35.1 53.9 2.0 35.4 55.0 2.1 35.6 56.1 2.2 35.8 57.1 2.3 36.1 57.7 2.4 36.3 58.2 2.5 36.5 58.7 2.6 36.7 59.2 2.7 36.8 59.6 Minimum Maximum 2.6 5.0 5.2 9.9 7.8 14.6 10.4 19.2 13.0 23.6 15.7 28.0 18.2 32.2 20.8 35.8 22.4 39.5 24.1 43.2 25.4 46.7 26.2 50.0 26.6 53.1 26.8 56.1 27.0 58.7 27.2 61.4 27.4 63.5 27.7 65.6 27.8 67.7 28.0 69.8 28.1 71.6 28.2 73.3 28.3 74.9 28.3 76.4 28.4 77.7 28.5 78.8 28.6 79.7 Table 9. Weak Driver Characteristics DDR SDRAM pullup Current (mA) Typical Typical Minimum Low High -3.5 -4.3 -2.6 -6.9 -8.2 -5.2 -10.3 -12.0 -7.8 -13.6 -15.7 -10.4 -16.9 -19.3 -13.0 -19.4 -22.9 -15.7 -21.5 -26.5 -18.2 -23.3 -30.1 -20.4 -24.8 -33.6 -21.6 -26.0 -37.1 -21.9 -27.1 -40.3 -22.1 -27.8 -43.1 -22.2 -28.3 -45.8 -22.3 -28.6 -48.4 -22.4 -28.7 -50.7 -22.6 -28.9 -52.9 -22.7 -28.9 -55.0 -22.7 -29.0 -56.8 -22.8 -29.2 -58.7 -22.9 -29.2 -60.0 -22.9 -29.3 -61.2 -23.0 -29.5 -62.4 -23.0 -29.5 -63.1 -23.1 -29.6 -63.8 -23.2 -29.7 -64.4 -23.2 -29.8 -65.1 -23.3 -29.9 -65.8 -23.3 Rev. 1.1 October 2008 Maximum -5.0 -9.9 -14.6 -19.2 -23.6 -28.0 -32.2 -35.8 -39.5 -43.2 -46.7 -50.0 -53.1 -56.1 -58.7 -61.4 -63.5 -65.6 -67.7 -69.8 -71.6 -73.3 -74.9 -76.4 -77.7 -78.8 -79.7 ...
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... K4H281638L Pulldown Characteristics for Matched Output Driver 0 Pullup Characteristics for Matched Output Driver Figure 6. I/V characteristics for input/output buffers:Pulldown(above) and pullup(below 1.0 2 DDR SDRAM ...
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... K4H281638L Pulldown Current (mA) Typical Typical Voltage (V) Low High 0.1 1.9 2.1 0.2 3.9 4.3 0.3 5.9 6.5 0.4 7.7 8.6 0.5 9.6 10.6 0.6 11.1 12.5 0.7 12.6 14.1 0.8 14.0 16.0 0.9 15.2 17.7 1.0 16.4 19.3 1.1 17.3 20.9 1.2 18.0 22.3 1.3 18.6 23.8 1.4 18.9 25.1 1.5 19.2 26.4 1.6 19.4 27.5 1.7 19.5 28.6 1.8 19.7 29.6 1.9 19.9 30.5 2.0 20.1 31.1 2.1 20.1 31.8 2.2 20.2 32.3 2.3 20.4 32.7 2.4 20.6 32.9 2.5 20.6 33.2 2.6 20.8 33.5 2.7 20.8 33.7 Minimum Maximum 1.5 2.6 2.9 5.4 4.4 8.2 5.9 10.9 7.3 13.3 8.9 15.9 10.3 18.3 11.8 20.3 12.7 22.3 13.6 24.5 14.4 26.4 14.9 28.3 15.0 30.1 15.2 31.8 15.3 33.2 15.4 34.8 15.5 36.0 15.7 37.1 15.7 38.3 15.9 39.5 15.9 40.5 16.0 41.5 16.0 42.4 16.0 43.2 16.1 44.0 16.1 44.6 16.2 45.1 Table 10. Matched Driver Characteristics DDR SDRAM pullup Current (mA) Typical Typical Minimum Low High -2.0 -2.4 -1.5 -3.9 -4.6 -2.9 -5.9 -6.8 -4.4 -7.7 -8.9 -5.9 -9.6 -10.9 -7.3 -11.0 -12.9 -8.9 -12.1 -15.0 -10.3 -13.2 -17.1 -11.6 -14.7 -19.0 -12.2 -14.7 -21.0 -12.4 -15.4 -22.7 -12.5 -15.7 -23.9 -12.6 -16.0 -25.1 -12.6 -16.2 -26.1 -12.7 -16.2 -26.9 -12.8 -16.4 -27.6 -12.9 -16.3 -28.2 -12.8 -16.4 -28.7 -12.9 -16.6 -29.0 -13.0 -16.5 -29.0 -12.9 -16.6 -29.0 -13.0 -16.7 -28.9 -13.0 -16.7 -28.5 -13.1 -16.8 -28.0 -13.2 -16.8 -27.6 -13.1 -16.9 -27.3 -13.2 -16.9 -27.0 -13.2 Rev. 1.1 October 2008 Maximum -2.5 -4.9 -7.2 -9.5 -11.9 -14.4 -16.8 -18.4 -20.2 -21.9 -23.5 -24.9 -26.1 -27.2 -28.0 -28.9 -29.5 -29.8 -30.5 -31.1 -31.4 -31.7 -31.9 -32.2 -32.2 -32.2 -32.0 ...