k4h281638l Samsung Semiconductor, Inc., k4h281638l Datasheet - Page 16

• Manufacturer Part Number: k4h281638l
• Description: 128mb L-die Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4H281638L
15.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A
IDD1 : Operating current: One bank operation
1. Typical Case: V
2. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
3. Timing patterns
IDD7A : Operating current: Four bank operation
1. Typical Case: V
2. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
4. Timing patterns
- B3(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=3*tCK, tRC = 10*tCK, tRAS=7*tCK
- CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK
- CD(250Mhz,CL = 3) : tCK = 4ns, CL = 3, BL = 4, tRCD = 4*tCK , tRC = 13*tCK, tRAS = 10*tCK
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT
- CC(200Mhz,CL = 3) : tCK = 5ns, BL = 4, tRRD=2*tCK, tRCD = 3*tCK , tRAS = 8*tCK
- CD(250Mhz,CL = 3) : tCK = 4ns, CL = 3, BL = 4, tRCD = 4*tCK , tRAS = 10*tCK
- B3(166Mhz,CL=2.5) : tCK=6ns, BL=4, tRRD=2*tCK, tRCD=3*tCK, tRAS=5*tCK
Read : A0 N N R0 N N N P0 N N - repeat the same timing with random address changing
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
Read : A0 N N N R0 N N N N N P0 N N - repeat the same timing with random address changing
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing
Read : A0 N N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing
*50% of data changing at every transfer
changing. lout = 0mA
per clock cycle. lout = 0mA
*50% of data changing at every burst
*50% of data changing at every transfer
*50% of data changing at every burst
*50% of data changing at every transfer
*50% of data changing at every transfer
Worst Case : V
Worst Case : V
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT
DD
DD
DD
DD
= 2.5V, T=25°C
= 2.5V, T=25°C
= 2.7V, T= 10°C
= 2.7V, T= 10°C
16 of 30
Rev. 1.1 October 2008
DDR SDRAM