k4h281638l Samsung Semiconductor, Inc., k4h281638l Datasheet - Page 20

• Manufacturer Part Number: k4h281638l
• Description: 128mb L-die Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

20.0 AC Timming Parameters & Specifications
K4H281638L
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK /CK
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Control & Address input pulse width
DQ & DM input pulse width
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
Power Down Exit
Parameter
TSOP
TSOP
CL=2.5
CL=3.0
Symbol
tWPREH
tDQSCK
tWPRES
tDQSQ
tDQSS
tDQSH
tWPST
tRPRE
tRPST
tDQSL
tXSNR
tXSRD
tPDEX
tDIPW
tRCD
tRRD
tWTR
tMRD
tREFI
tQHS
tRFC
tRAS
tDSS
tDSH
tRAP
tIPW
tDAL
tWR
tCH
tQH
tRC
tRP
tCK
tCL
tAC
tHZ
tDS
tDH
tHP
tLZ
tIS
tIH
tIS
tIH
(DDR500@CL=3.0)
(tWR/tCK)
or tCHmin
(tRP/tCK)
tCLmin
-tQHS
Min
0.45
0.45
0.85
0.35
1.75
-0.6
-0.6
-0.7
-0.7
200
0.9
0.4
0.2
0.2
0.4
0.4
0.9
0.9
0.9
0.9
0.4
0.4
2.2
tHP
0.4
52
60
36
16
16
12
12
75
16
2
6
4
0
8
+
1
-
CD
20 of 30
Max
0.55
0.55
+0.6
+0.6
1.15
+0.7
+0.7
15.6
70K
0.4
1.1
0.6
0.4
0.6
10
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(DDR400@CL=3.0)
or tCHmin
(tWR/tCK)
(tRP/tCK)
tCLmin
-0.65
-0.65
-tQHS
Min
0.45
0.45
0.72
0.25
0.35
0.35
1.75
-0.6
-0.7
200
0.9
0.4
0.2
0.2
0.6
0.6
0.7
0.7
0.4
0.4
2.2
tHP
0.4
55
70
40
15
15
10
15
10
75
15
2
6
5
0
+
-
1
CC
+0.65
+0.65
Max
0.55
0.55
+0.6
+0.7
1.28
15.6
70K
0.4
1.1
0.6
0.5
0.6
10
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(DDR333@CL=2.5)
or tCHmin
(tWR/tCK)
(tRP/tCK)
tCLmin
-tQHS
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.75
0.75
0.45
0.45
1.75
-0.6
-0.7
-0.7
-0.7
200
0.9
0.4
0.2
0.8
0.8
0.4
0.2
2.2
tHP
60
72
42
18
18
12
15
12
75
18
1
6
0
+
1
-
-
Rev. 1.1 October 2008
B3
DDR SDRAM
Max
0.55
0.55
+0.6
+0.7
0.45
1.25
+0.7
+0.7
15.6
0.55
70K
1.1
0.6
0.6
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
15, 17~19
15, 17~19
16~19
16~19
20, 21
Note
j, k
j, k
22
13
18
18
14
21
21
12
23
11
11