k4h281638l Samsung Semiconductor, Inc., k4h281638l Datasheet - Page 4

• Manufacturer Part Number: k4h281638l
• Description: 128mb L-die Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

2.0 Ordering Information
3.0 Operating Frequencies
K4H281638L
1.0 Key Features
• V
• V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• Auto & Self refresh
•
• Maximum burst refresh cycle : 8
• 66pin TSOP II
•
15.6us refresh interval(4K/64ms refresh)
RoHS compliant
DD
DD
-. Read latency : DDR333(2.5 Clock), DDR400(3 Clock), DDR500(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
Speed @CL2.5
Speed @CL2
Speed @CL3
CL-tRCD-tRP
: 2.5V ± 0.2V, V
: 2.5V ± 5%, V
K4H281638L-LCCD
K4H281638L-LCCC
K4H281638L-LCB3
Part No.
Lead-Free and Halogen-Free
DDQ
DDQ
: 2.5V ± 5% for DDR500
: 2.5V ± 0.2V for DDR333, 400
CD(DDR500@CL=3)
166MHz
250MHz
8M x 16
3-4-4
Org.
N/A
package
CD(DDR500@CL=3)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Max Freq.
4 of 30
CC(DDR400@CL=3)
166MHz
200MHz
3-3-3
N/A
Interface
SSTL2
Lead-Free & Halogen-Free
66pin TSOP II
Rev. 1.1 October 2008
Package
B3(DDR333@CL=2.5)
DDR SDRAM
166MHz
2.5-3-3
N/A
-
Note