k4h281638l Samsung Semiconductor, Inc., k4h281638l Datasheet - Page 9

• Manufacturer Part Number: k4h281638l
• Description: 128mb L-die Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

DDR SDRAM operation. The mode register is written by asserting low on CS, RAS, CAS, WE and BA0(The DDR SDRAM should be in
* RFU(Reserved for future use)
7.2 Mode Register Definition
Mode Register Set(MRS)
mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different appli-
cations. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper
all bank precharge with CKE already high prior to writing into the mode register). The states of address pins A0 ~ A11 in the same cycle
as CS, RAS, CAS, WE and BA0 going low are written in the mode register. Two clock cycles are requested to complete the write opera-
tion in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst
length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test
mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst
lengths, addressing modes and CAS latencies.
K4H281638L
BA0
RFU
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing
must stay "0" during MRS cycle.
BA
0
1
1
(Existing)MRS Cycle
Extended Funtions(EMRS)
BA
0
0
An ~ A0
A
11
Note : *1 A12 is used for 256Mb only. That is 128Mb uses A0~A11
A
0
1
8
RFU
A
10
DLL Reset
Yes
No
A
9
DLL
A
CAS Latency
8
A
0
0
0
0
1
1
1
1
6
TM
A
A
7
0
1
7
A
0
0
1
1
0
0
1
1
5
A
6
Normal
mode
A
CAS Latency
0
1
0
1
0
1
0
1
Test
4
9 of 30
A
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Latency
5
2.5
3
A
4
A
0
1
3
BT
A
Burst Length
3
A
0
0
0
0
1
1
1
1
2
Burst Type
Sequential
Interleave
A
2
A
Burst Length
0
0
1
1
0
0
1
1
1
A
A
1
0
1
0
1
0
1
0
1
0
Rev. 1.1 October 2008
A
Sequential
0
Reserve
Reserve
Reserve
Reserve
Reserve
DDR SDRAM
2
4
8
Burst Length
Address Bus
Mode Register
Interleave
Reserve
Reserve
Reserve
Reserve
Reserve
2
4
8