k7r643684m-fi300 Samsung Semiconductor, Inc., k7r643684m-fi300 Datasheet
k7r643684m-fi300
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k7r643684m-fi300 Summary of contents
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... K7R643684M K7R641884M 72Mb QDRII SRAM Specification 165 FBGA with Pb & Pb-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ...
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... K7R643684M K7R641884M Document Title 2Mx36-bit, 4Mx18-bit QDR Revision History Rev. No. History 0.0 1. Initial document. 0.1 1. Update AC timing characteristics. 2. Change the JTAG instruction coding. 0.2 1. Change the AC timing characteristics. (-25/-20 parts) 2. Correct the overshoot and undershoot timing diagrams. 3. Change the JTAG Block diagrams. 4. Update the Boundary scan exit order. ...
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... QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology. 2Mx36 & 4Mx18 QDR II b4 SRAM TM Org. K7R643684M-F(E)C(I)30 K7R643684M-F(E)C(I)25 X36 K7R643684M-FC(I)20 K7R643684M-FC(I)16 K7R641884M-F(E)C(I)30 X18 K7R641884M-F(E)C(I)25 K7R641884M-FC(I)20 K7R641884M-FC(I)16 * -F(E)C(I) F(E) [Package type]: E-Pb. Free, F-Pb C(I) [Operating Temperature]: C-Commercial, I-Industrial ...
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... ZQ V 5F,7F,5G,7G,5H,7H,5J,7J,5K, 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L DDQ V 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M,8M,4N,8N SS TMS TDI TCK TDO NC Notes cannot be set to V REF 2. When ZQ pin is directly connected Not connected to chip pad internally. 2Mx36 & 4Mx18 QDR K7R643684M(2Mx36 ...
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... K7R643684M K7R641884M PIN CONFIGURATIONS (TOP VIEW) K7R641884M(4Mx18 NC/SA D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H Doff V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 Q16 ...
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... And pipelined data are transferred out of device on every rising edge of both C and C clocks. In case C and C tied to high, output data are triggered by K and K instead of C and C. When the R is disabled after a read operation, the K7R643684M and K7R641884M will first complete burst read operation before entering into deselect mode at the next K clock rising edge. ...
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... K7R643684M K7R641884M Single Clock Mode The K7R643684M and K7R641884M can be operated with the single clock pair K and K, instead for output clocks. To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high during operation. ...
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... K7R643684M K7R641884M Detail Specification of Power-Up Sequence in QDRII SRAM QDRII SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. • Power-Up Sequence 1. Apply power and keep Doff at low state (All other inputs may be undefined) - Apply VDD before VDDQ - Apply VDDQ before VREF or the same time with VREF 2 ...
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... K7R643684M K7R641884M TRUTH TABLES SYNCHRONOUS TRUTH TABLE D(A1) Previous Stopped X X state ↑ ↑ Din ↑ K(t+1) Notes means "Don′t Care". 2. The rising edge of clock is symbolized by (↑ Before enter into clock stop status, all pending read and write operations will be completed. ...
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... K7R643684M K7R641884M ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on V Supply Relative Voltage on V Supply Relative to V DDQ Voltage on Input Pin Relative Storage Temperature Operating Temperature (Commercial / Industrial) Storage Temperature Range Under Bias *Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... K7R643684M K7R641884M AC ELECTRICAL CHARACTERISTICS PARAMETER Input High Voltage Input Low Voltage Notes: 1. This condition is for AC function test only, not for AC parameter test maintain a valid level, the transition edge of the input must: a) Sustain a constant slew rate from the current AC level through the target AC level, V ...
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... K7R643684M K7R641884M THERMAL RESISTANCE PRMETER Junction to Ambient Junction to Case Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site x θ thermal impedance PIN CAPACITANCE PRMETER Address Control Input Capacitance Input and Output Capacitance Clock Capacitance Note: 1. Parameters are tested with RQ=250Ω ...
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... K7R643684M K7R641884M APPLICATION INRORMATION Vt R Data In Data Out Address MEMORY CONTROLLER Return CLK Vt Source CLK Return CLK Vt Source CLK R=50Ω Vt=V SRAM1 Input CQ SRAM1 Input CQ SRAM4 Input CQ SRAM4 Input CQ 2Mx36 & 4Mx18 QDR ZQ R=250Ω SRAM ...
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... K7R643684M K7R641884M TIMING WAVE FORMS OF READ AND NOP READ t KHKH t KLKH KHKH KHKL IVKH KHIX R Q (Data Out) t KHKH t KLKH KHKL Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0. ...
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... K7R643684M K7R641884M TIMING WAVE FORMS OF READ, WRITE AND NOP READ (Data In) D (Data Out Note address A3=A2, data Q3-1=D2-1, data Q3-2=D2-2, data Q3-3=D2-3, data Q3-4=D2-4 Write data is forwarded immediately as read results. 2.BWx assumed active. 2Mx36 & 4Mx18 QDR WRITE READ A2 A3 ...
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... K7R643684M K7R641884M IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control ...
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... K7R643684M K7R641884M SCAN REGISTER DEFINITION Part Instruction Register 2Mx36 3 bits 4Mx18 3 bits ID REGISTER DEFINITION Revision Number Part (31:29) 2Mx36 000 4Mx18 000 Note: Part Configuration /def=011 for 72Mb, /wx=11 for x36, 10 for x18 /t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O ...
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... K7R643684M K7R641884M JTAG DC OPERATING CONDITIONS Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage (IOH=-2mA) Output Low Voltage(I =2mA) OL Note: 1. The input level of SRAM pin is to follow the SRAM DC specification JTAG AC TEST CONDITIONS Parameter Input High/Low Level ...
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... K7R643684M K7R641884M 165 FBGA PACKAGE DIMENSIONS 15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array Symbol Value Units 15 ± 0 ± 0.1 B 1.3 ± 0.1 C 0.35 ± 0.05 D 2Mx36 & 4Mx18 QDR Note Symbol SRAM Top View ...