k7r643684m-fi300 Samsung Semiconductor, Inc., k7r643684m-fi300 Datasheet - Page 8

• Manufacturer Part Number: k7r643684m-fi300
• Description: 2mx36-bit, 4mx18-bit Qdrtm Ii B4 Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7R643684M
QDRII SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
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* Notes: When the operating frequency is changed, DLL reset should be required again.
K7R641884M
Detail Specification of Power-Up Sequence in QDRII SRAM
Power up & Initialization Sequence (Doff pin Fixed high, Clock controlled)
Status
Power up & Initialization Sequence (Doff pin controlled)
Status
Power-Up Sequence
DLL Constraints
V
V
K,K
V
V
REF
K,K
DDQ
V
V
Doff
DD
DDQ
REF
DD
After DLL reset again, the minimum 2048 cycles of clock input is needed to lock the DLL.
1. Apply power and keep Doff at low state (All other inputs may be undefined)
2. Just after the stable power and clock(K,K), take Doff to be high.
3. The additional 2048 cycles of clock input is required to lock the DLL after enabling DLL
1. DLL uses either K clock as its synchronizing input, the input should have low phase jitter which is specified as TK var.
2. The lower end of the frequency at which the DLL can operate is 120MHz.
3. If the incoming clock is unstable and the DLL is enabled, then the DLL may lock onto a wrong frequency
* Notes: If you want to tie up the Doff pin to High with unstable clock, then you must stop the clock for a few seconds
(Min. 30ns) to reset the DLL after it become a stable clock status.
and this may cause the failure in the initial stage.
- Apply VDD before VDDQ
- Apply VDDQ before VREF or the same time with VREF
Power-Up
Power-Up
Unstable
CLKstage
Unstable
CLKstage
- 8 -
Stop Clock
2Mx36 & 4Mx18 QDR
Min 30ns
must be stable
Inputs Clock
DLL Locking Range
must be stable
Inputs Clock
1024 cycle
DLL Locking Range
1024 cycle
Rev. 1.3 March 2007
TM
II b4 SRAM
Any
Command
Any
Command