k7r643684m-fi300 Samsung Semiconductor, Inc., k7r643684m-fi300 Datasheet - Page 6

• Manufacturer Part Number: k7r643684m-fi300
• Description: 2mx36-bit, 4mx18-bit Qdrtm Ii B4 Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7R643684M
Read Operations
K7R641884M
GENERAL DESCRIPTION
Read cycles are initiated by activating R at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 4-bit burst DDR operation, it will access four 36-bit or 18-bit data words with each read command.
The first pipelined data is transferred out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
The process continues until all four data are transferred.
Continuous read operations are initiated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K instead of C and C.
When the R is disabled after a read operation, the K7R643684M and K7R641884M will first complete burst read operation
before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
Write Operations
The K7R643684M and K7R641884M are 75,497,472-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs.
They are organized as 2,097,152 words by 36bits for K7R643684M and 4,194,304 words by 18 bits for K7R641884M.
The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports
with the same cycle. Memory bandwidth is maximized as data can be transferred into SRAM on every rising edge of K and K,
and transferred out of SRAM on every rising edge of C and C.
And totally independent read and write ports eliminate the need for high speed bus turn around.
Address for read and write are latched on alternate rising edges of the input clock K.
Data inputs, and all control signals are synchronized to the input clock (K or K).
Normally data outputs are synchronized to output clocks (C and C), but when C and C are tied high,
the data outputs are synchronized to the input clocks (K and K).
Read data are referenced to echo clock (CQ or CQ) outputs.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fixed to 4-bit sequential for both read and write operations, requiring tow full clock bus cycles.
Any request that attempts to interrupt a burst operation in progress is ignored.
Synchronous pipeline read and late write enable high speed operations.
Simple depth expansion is accomplished by using R and W for port selection.
Byte write operation is supported with BW
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system.
The K7R643684M and K7R641884M are implemented with SAMSUNG's high performance 6T CMOS technology
Write cycles are initiated by activating W at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with K clock.
For 4-bit burst DDR operation, it will write four 36-bit or 18-bit data words with each write command.
The first "late" data is transferred and registered in to the device synchronous with next K clock rising edge.
Next burst data is transferred and registered synchronous with following K clock rising edge.
The process continues until all four data are transferred and registered.
Continuous write operations are initiated with K rising edge.
And "late writed" data is presented to the device on every rising edge of both K and K clocks.
The device disregards input data presented on the same cycle W disabled.
When the W is disabled after a read operation, the K7R643684M and K7R641884M will first complete burst read operation
before entering into deselect mode at the next K clock rising edge.
The K7R643684M and K7R641884M support byte write operations.
With activating BW
In K7R641884M, BW
And in K7R643684M BW
and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
0
or BW
0
controls write operation to D0:D8, BW
2
1
controls write operation to D18:D26, BW
(BW
2
or BW
3)
0
in write cycle, only one byte of input data is presented.
and BW
1
(BW
2
and BW
1
controls write operation to D9:D17.
- 6 -
3
3)
2Mx36 & 4Mx18 QDR
controls write operation to D27:D35.
pins.
Rev. 1.3 March 2007
TM
II b4 SRAM