cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 271
cn8236
Manufacturer Part Number
cn8236
Description
Atm Servicesar Plus With Xbr Traffic Management
Manufacturer
Mindspeed Technologies
Datasheet
1.CN8236.pdf
(443 pages)
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CN8236
ATM ServiceSAR Plus with xBR Traffic Management
28236-DSH-001-B
of systems, the SRAM requirements is considerably less. The implications of this
are that the PBSEL[1:0] inputs can be driven by lower order address lines, and
there are less than 17 address lines to buffer. Therefore, in most applications, the
data transceivers can utilize two x_16 parts, such as a 74ABT16245, and the
address buffer can utilize a single x_16 74ABT16244.
NOTE:
10.5 Local Processor Operating Mode
The major difference between the i80960Jx processor and the i80960CA is that
the i80960Jx utilizes a multiplexed address/data bus structure, while the
i80960CA/CF is non-multiplexed. However, in the CN8236 system, the
de-multiplexing of address/data takes place on the processor side of the address
buffers and, therefore, does not affect the CN8236. Otherwise, the i80960Jx has
the same bus control signals as the i80960CA/CF with the exception of the
WAIT* signal, which the i80960Jx does not possess. The insertion of wait states,
if required, must be accomplished by an external memory controller, which in any
case, is required for a i80960Jx implementation.
This configuration is for addressing the entire 8 MB of SRAM. In the majority
The i960CA/CF signals a failure of its internal self-test upon reset or
power-up, by asserting its FAIL* output. This line is connected to the
PFAIL* pin of the CN8236, and the status of this pin is reflected in the
Host Interrupt Status register [HOST_ISTAT0; 0xC0].
Mindspeed Technologies
™
10.5 Local Processor Operating Mode
10.0 Local Processor Interface
10-13
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