cn8236 Mindspeed Technologies, cn8236 Datasheet - Page 331

• Manufacturer Part Number: cn8236
• Description: Atm Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
0xac
The SCH_CTRL register defines the configured schedule slot and priority and VBR offsets when 16 priority
queues are used.
0xb0
This register sets the maximum number of ABR VCCs being used and specifies the MAX_BEHIND value. The
MAX_BEHIND value specifies the number of slots in the schedule table; the schedule table entry pointer can
fall behind. MAX_BEHIND should be set to 0 for all applications, except special multi-PHY DSL applications.
28236-DSH-001-B
31–27
22–18
16–15
14–12
11–10
31–24
9–6
5–4
3–0
Bit
Bit
26
25
24
23
17
—
—
Scheduler Control Register (SCH_CTRL)
Maximum ABR VCC_INDEX Register (SCH_ABR_MAX)
Field
Field
Size
Size
5
1
1
1
1
5
1
2
3
2
4
2
4
8
Reserved
USE_SCHREF
EXTERNAL_SCH
NCR_EN_DEST
NCR_EN_SRC
NCR_STAT_ID
EN_NCR_STAT
Reserved
SLOT_DEPTH
Reserved
TUN_PRI0_OFFSET
Reserved
VBR_OFFSET
Reserved
Name
Name
Mindspeed Technologies
Program and read as 0.
If logic high, the SCHREF input is used as the clock for defining a schedule
table slot period in conjunction with SLOT_PER. If logic low, SYSCLK is
used.
If logic high, scheduling priority is granted to externally scheduled traffic.
See
Global enable for destination ACR notification.
Global enable for source ACR notification.
Identifies the status queue to be used for both source and destination
ACR/ER notification when EN_NCR_STAT is asserted.
Enable global status queue for both source and destination ACR/ER
notification.
Program and read as 0.
Depth of the schedule slot is set to 1 + SLOT_DEPTH words. Active only if
USE_SCH_CTRL is asserted.
Program and read as 0.
Offset from the TUN_PRI_0 field in the schedule table and CBR VCC table.
Active only if USE_SCH_CTRL is asserted.
Program and read as 0.
Offset from schedule slot priority to general priority. Active only if
USE_SCH_CTRL is asserted.
Set to 0.
NOTE:
Chapter
Must be set to 0 during initialization unless using an
external scheduler clock.
13.0.
™
Description
Description
14.0 CN8236 Registers
14.4 Scheduler Registers
14-15