A40MX02-PL208A ACTEL [Actel Corporation], A40MX02-PL208A Datasheet - Page 44

• Manufacturer Part Number: A40MX02-PL208A
• Description: 40MX and 42MX Automotive FPGA Families
• Manufacturer: ACTEL [Actel Corporation]

Table 1-13 • A42MX24 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, V
1 -4 0
Parameter
TTL Output Module Timing
t
t
t
t
t
t
t
t
t
t
t
t
d
d
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
5. Delays based on 35 pF loading.
DLH
DHL
ENZH
ENZL
ENHZ
ENLZ
GLH
GHL
LSU
LH
LCO
ACO
TLH
THL
40MX and 42MX Automotive FPGA Families
device performance. Post-route timing analysis or simulation is required to determine actual performance.
obtained from the Timer tool.
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
G-to-Pad LOW
I/O Latch Set-Up
I/O Latch Hold
I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading
Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading
Capacity Loading, LOW to HIGH
Capacity Loading, HIGH to LOW
5
PD1
+ t
RD1
CCA
+ t
= 4.75V, T
PDn
, t
Description
CO
+ t
J
= 125°C
RD1
+ t
v3.1
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
Min.
0.8
0.0
Std. Speed
Max.
17.8
0.06
0.05
4.1
4.8
4.3
4.8
8.6
8.0
4.9
4.9
9.2
Units
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns