A40MX02-PL208A ACTEL [Actel Corporation], A40MX02-PL208A Datasheet - Page 34

• Manufacturer Part Number: A40MX02-PL208A
• Description: 40MX and 42MX Automotive FPGA Families
• Manufacturer: ACTEL [Actel Corporation]

Table 1-10 • A40MX04 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, V
1 -3 0
Parameter
Logic Module Propagation Delays
t
t
t
t
t
Logic Module Predicted Routing Delays
t
t
t
t
t
Logic Module Sequential Timing
t
t
t
t
t
t
t
f
Input Module Propagation Delays
t
t
Input Module Predicted Routing Delays
t
t
t
t
t
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this
4. Delays based on 35 pF loading.
PD1
PD2
CO
GO
RS
RD1
RD2
RD3
RD4
RD8
SUD
HD
SUENA
HENA
WCLKA
WASYN
A
MAX
INYH
INYL
IRD1
IRD2
IRD3
IRD4
IRD8
40MX and 42MX Automotive FPGA Families
3
device performance. Post-route timing analysis or simulation is required to determine actual performance.
macro.
Single Module
Dual-Module Macros
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Flip-Flop (Latch) Data Input Set-Up
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active Pulse
Flip-Flop (Latch)
Flip-Flop Clock Input Period
Flip-Flop (Latch) Clock Frequency
Pad-to-Y HIGH
Pad-to-Y LOW
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2
1
CC
= 4.75V, T
1
1
Description
J
= 125°C
v3.1
Min.
5.4
0.0
5.4
0.0
5.8
5.8
8.7
Std. Speed
Max.
10.2
116
2.2
4.7
2.2
2.2
2.2
2.4
3.4
4.3
5.2
9.0
1.3
1.2
3.7
4.6
5.6
6.5
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns