bt829bkrf ETC-unknow, bt829bkrf Datasheet - Page 15

• Manufacturer Part Number: bt829bkrf
• Description: Video Streamii Decoders
• Manufacturer: ETC-unknow

Bt829B/827B
VideoStream II Decoders
1.1.5 Scaling and Cropping
1.1.6 Input Interface
1.1.7 Output Interface
The Bt829B can reduce the video image size in both horizontal and vertical direc-
tions independently using arbitrarily selected scaling ratios. The X and Y dimen-
sions can be scaled down to one-sixteenth of the full resolution. Horizontal
scaling is implemented with a 6-tap interpolation filter, while up to 5-tap interpo-
lation is used for vertical scaling with a line store. The Bt827B supports vertical
scaling by line-dropping.
to reduce the number of active scan lines and active horizontal pixels per line.
reduces video bandwidth by allowing frames or fields to be dropped from a video
sequence at regular but arbitrarily selected intervals.
Analog video signals are input to the Bt829B/827B via a four-input multiplexer
that can select between four composite source inputs or between three composite
and a single S-Video input source. When an S-Video source is input to the
Bt829B, the luma component is fed through the input analog multiplexer, and the
chroma component is fed directly into the C-input pin. An AGC circuit enables
the Bt829B/827B to compensate for reduced amplitude in the analog signal input.
and two clock output pins. One pair of crystal pins is for connection to a
28.64 MHz (8*NTSC Fsc) crystal which is selected for NTSC operation. The
other is for PAL operation with a 35.47 MHz (8*PAL Fsc) crystal. Either of the
two crystal frequencies can be selected to generate CLKx1 and CLKx2 output
signals. CLKx2 operates at the full crystal frequency (8*Fsc), whereas CLKx1
operates at half the crystal frequency (4*Fsc). Either fundamental or third har-
monic crystals may be used. Alternatively, CMOS oscillators may be used.
The Bt829B and Bt827B support a Synchronous Pixel Interface (SPI) mode.
When the pixel output port is configured to operate 8-bits wide, 8 bits of chromi-
nance data are output on the first clock cycle followed by 8 bits of luminance data
on the next clock cycle for each pixel. Two clocks are required to output one pixel
in this mode, thus a 2x clock is used to output the data.
tion to the active pixels synchronous with CLKX1 (16-bit mode) or CLKX2 (8-
bit mode). It is also possible to insert control codes into the pixel stream using
chrominance and luminance values that are outside the allowable chroma and
luma ranges. These control codes can be used to flag video events such as
ACTIVE, HRESET, and VRESET. Decoding these video events downstream
enables the video controller to eliminate pins required for the corresponding
video control signals. Both Bt829B and Bt827B can output (or receive) all digital
timing, clock, and data signals at either 5 V or 3.3 V levels for connection to 5 V
or 3.3 V graphics/video controllers.
The video image can be arbitrarily cropped by programming the ACTIVE flag
The Bt829B and Bt827B also support a temporal decimation feature that
The clock signal interface consists of two pairs of pins for crystal connection
The SPI supports a YCrCb 4:2:2 data stream over an 8- or 16-bit-wide path.
The Bt829B/827B outputs all horizontal and vertical blanking pixels in addi-
D829BDSA
1.0 Functional Description
1.1 Functional Overview
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