bt829bkrf ETC-unknow, bt829bkrf Datasheet - Page 70
bt829bkrf
Manufacturer Part Number
bt829bkrf
Description
Video Streamii Decoders
Manufacturer
ETC-unknow
Datasheet
1.BT829BKRF.pdf
(127 pages)
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2.0 Electrical Interfaces
2.2 Output Interface
Figure 2-11. Video Timing in SPI Modes 1 and 2
Notes: (1). HRESET precedes VRESET by two clock cycles at the beginning of fields 1, 3, 5, and 7 to facilitate external field
HRESET
HRESET
VRESET
FIELD
ACTIVE
VRESET
FIELD
ACTIVE
2. ACTIVE pin may be programmed to be composite ACTIVE or horizontal ACTIVE.
3. ACTIVE, HRESET, VRESET and FIELD are shown with their default polarity. The polarity is programmable via the
4. FIELD transitions with the end of horizontal active video, defined by HDELAY and HACTIVE.
generation.
VPOLE register.
(1)
Beginning of Fields 1, 3, 5, 7
Beginning of Fields 2, 4, 6, 8
2–6 scan lines
2–6 scan lines
D829BDSA
VDELAY/2 scan lines
VDELAY/2 scan lines
VideoStream II Decoders
Bt829B/827B
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