bt829bkrf ETC-unknow, bt829bkrf Datasheet - Page 19

• Manufacturer Part Number: bt829bkrf
• Description: Video Streamii Decoders
• Manufacturer: ETC-unknow

Bt829B/827B
VideoStream II Decoders
Table 1-2. Pin Descriptions Grouped By Pin Function (2 of 4)
82
79
83
94
98
78
89
2–9
22–29
84
87
Pin #
I/O
I/O
O
O
O
O
O
O
O
O
O
I
Pin Name
VD[15:8]
CCVALID
HRESET
VRESET
CBFLAG
VD[7:0]
DVALID
ACTIVE
FIELD
QCLK
OE
Horizontal Reset Output (TTL compatible). This signal indicates the beginning of a
new line of video. This signal is 64 CLKx1 clock cycles wide. The falling edge of this
output indicates the beginning of a new scan line of video. This pin may be defined in
pixels as opposed to CLKx1 cycles. Refer to the HSFMT bit in the VTC register.
Note: The polarity of this pin is programmable through the VPOLE register.
Vertical Reset Output (TTL compatible). This signal indicates the beginning of a new
field of video. This signal is output coincident with the rising edge of CLKx1, and is
normally 6 lines wide. The falling edge of VRESET indicates the beginning of a new
field of video.
Note: The polarity of this pin is programmable through the VPOLE register.
Active Video Output (TTL compatible). This pin can be programmed to output the
composite active or horizontal active signal via the VTC register. It is a logical high
during the active/viewable periods of the video stream. The active region of the video
stream is programmable.
Note: The polarity of this pin is programmable through the VPOLE register.
Qualified Clock Output. This pin provides a rising edge only during valid, active pixel
data. This output is generated from CLKx1 (or CLKx2 in 8-bit mode), DVALID and, if
programmed, ACTIVE. The phase of QCLK is inverted from the CLKx1 (or CLKx2) to
ensure adequate setup and hold time with respect to the data outputs. QCLK is not
output during control codes when using SPI mode 2.
Output Enable Control (TTL compatible). All video timing unit output pins and all
clock interface output pins contain valid data following the rising edge of CLKx2,
after OE has been asserted low. This function is asynchronous. The three-stated pins
include: VD[15:0], HRESET , VRESET, ACTIVE, DVALID, CBFLAG, FIELD, QCLK,
CLKx1, and CLKx2. See the OES bits in the OFORM register to disable subgroups of
output pins.
Odd/Even Field Output (TTL compatible). A high state on the FIELD pin indicates that
an odd field is being digitized.
Note: The polarity of this pin is programmable through the VPOLE register.
Cb Data Identifier (TTL compatible). A high state on this pin indicates that the current
chroma byte contains Cb chroma information.
Note: The polarity of this pin is programmable through the VPOLE register.
Digitized Video Data Outputs (TTL compatible). VD[0] is the least significant bit of
the bus in 16-bit mode. VD[8] is the least significant bit of the bus in 8-bit mode. The
information is output with respect to CLKx1 in 16-bit mode, and CLKx2 in 8-bit
mode. In mode 2, this port is configured to output control codes as well as data.
When data is output in 8-bit mode using VD[15:8], VD[7:0] can be used as general
purpose I/O pins. See the P_IO register.
Data Valid Output (TTL compatible). This pin indicates when a valid pixel is being
output onto the data bus. The Bt829B digitizes video at eight times the subcarrier
rate, and outputs scaled video. Therefore, there are more clocks than valid data.
DVALID indicates when valid pixel data is being output.
A logical low on this pin indicates that the CC FIFO is half full (8 characters). This pin
may be disabled. This open drain output requires a pullup resistor for proper opera-
tion. However, if closed captioning is not implemented, this pin may be left uncon-
nected.
Note: The polarity of this pin is programmable through the VPOLE register.
Video Timing Unit Pins
D829BDSA
Description
1.0 Functional Description
1.2 Pin Descriptions
9