cxd2548r Sony Electronics, cxd2548r Datasheet - Page 100

• Manufacturer Part Number: cxd2548r
• Description: Cd Digital Signal Processor With Built-in Digital Servo And Dac
• Manufacturer: Sony Electronics

$3F
AGG4:
XT4D, XT2D:
DRR2 to DRR0: Partially clears the Data RAM values (0 write).
ASFG:
LPAS:
SRO1, SRO0:
AGHF:
COT2:
D15
0
AGG4 XT4D XT2D
D14
D13
This varies the amplitude of the internally generated sine wave using the AGGF and AGGT
commands during AGC.
When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below.
MCK (digital servo master clock) frequency division setting
This command forcibly sets the frequency division ratio to 1/2 or 1/4 when MCK is generated
from the signal input to the FSTI pin.
The following values are cleared when set to 1 (on) respectively; default = 0
DRR2: M08, M09, M0A
DRR1: M00, M01, M02
DRR0: M00, M01, M02 only when LOCK = low
Note) Set DRR1 and DRR0 for 50µs or more.
When vibration detection is performed during anti-shock circuit operation, FCS servo filter is
forcibly set to gain normal status.
On when set to 1; default = 0
Built-in analog buffer low-current consumption mode
This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE
input by using a single operational amplifier.
On when set to 1; default = 0
Note) When using this mode, firstly check whether each error signal is properly A/D converted
These commands are used to output various data continuously externally which have been
specified with the $39 command. (However, D15 (DAC) of $39 must be set to 1.)
Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by setting
these commands to 1 respectively. The default is 0, 0.
The output pins for each case are shown below.
(See "Description of Data Readout" on the following page.)
This halves the frequency of the internally generated sine wave during AGC.
The STZC signal is output from COUT by setting D0 to 1.
(STZC: TZC signal generated by sampling the TE signal at 700kHz)
SOCK
XOLT
SOUT
AGGF (MSB)
XT4D
0
0
1
D12
using the SRO1 and SRO0 commands of $3F.
0
0
1
1
D11
XT2D
0
0
1
0
SRO1 = 1
XUGF
GFS
GTOP
DRR2 DRR1 DRR0
AGGT (LSB)
D10
According to XTSL (default)
1/2
1/4
0
1
0
1
Frequency division ratio
D9
D8
TE/FE input conversion
– 100 –
D7
0
125 [mV]
250 [mV]
31 [mV]
63 [mV]
ASFG
D6
D5
0
LPAS SRO1 SRO0 AGHF COT2
These settings are the same as
for both focus auto gain control
and tracking auto gain control.
D4
D3
D2
D1
CXD2548R
D0