cxd2548r Sony Electronics, cxd2548r Datasheet - Page 99

• Manufacturer Part Number: cxd2548r
• Description: Cd Digital Signal Processor With Built-in Digital Servo And Dac
• Manufacturer: Sony Electronics

$3E
F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage
T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage
F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage
T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage
Note) Filter first- and third-stage quasi double accuracy settings can be set individually.
DFIS:
TLCD:
RFLP:
MIRI:
XT1D:
F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD RFLP
D15
See "FILTER Composition" at the end of this specification concerning quasi double-accuracy.
D14
D13
On when set to 1; default = 0.
F1NM: Gain normal
F1DM: Gain down
On when set to 1; default = 0.
T1NM: Gain normal
T1UM: Gain up
On when set to 1; default = 0.
Generally, the advance amount of the phase becomes large by partially setting the FCS servo
third-stage filter which is used as the phase compensation filter to double accuracy.
F3NM: Gain normal
F3DM: Gain down
On when set to 1; default = 0.
Generally, the advance amount of the phase becomes large by partially setting the TRK servo
third-stage filter which is used as the phase compensation filter to double accuracy.
T3NM: Gain normal
T3UM: Gain up
FCS hold filter input extraction node selection
0: M05 (Data RAM address 05); default
1: M04 (data RAM address 04)
This command masks the TLC2 command set by D2 of $38 only when FOK is low.
On when set to 1; default = 0
This command passes the signal obtained from the RFDC pin through the LPF (low-pass filter)
before the built-in A/D converter.
0: LPF off; default
1: LPF on
MIRR input switching.
The MIRR signal can be input from an external source. When D1 is 0, the MIRR signal is used
internally as usual. When D1 = 1, the MIRR signal can be input from an external source
through the MIRR pin.
The clock input from FSTI can be used as the master clock for the servo block regardless of the
XTSL pin, XT2D and XT4D by setting D0 to 1.
D12
D11
D10
D9
D8
– 99 –
D7
D6
D5
D4
0
D3
0
D2
0
MIRI XT1D
D1
CXD2548R
D0