cxd2548r Sony Electronics, cxd2548r Datasheet - Page 77

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cxd2548r

Manufacturer Part Number
cxd2548r
Description
Cd Digital Signal Processor With Built-in Digital Servo And Dac
Manufacturer
Sony Electronics
Datasheet

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<Measurement>
• VC AVRG
• FE AVRG
• TE AVRG
• RE AVRG
An example of sending AVRG measurement and compensation commands is shown below.
(Example) $380800 (RF Avrg. measurement on)
An interval of 5.8ms or more must be maintained between each command, or the SENS pin must be monitored
to confirm that the previous command has been completed before the next AVRG command is sent.
<Compensation>
See Fig. 4-2 for the contents of each compensation below.
• RFLC
• TCL0
• TCL1
• VCLC
• FLC1
• FLC0
The offset can be canceled by measuring the VC level which is the center voltage for the system and using
that value to apply compensation to each input error signal.
The FE signal DC level is measured. In addition, compensation is applied to the FZC comparator level output
from the SENS pin during FCS SEARCH (focus search) using these measurement results.
The TE signal DC level is measured.
The MIRR, DFCT and FOK signals are generated from the RF signal. However, the FOK signal is generated
by comparing the RF signal at a certain level, so that it is necessary to establish a zero level which becomes
the comparator level reference. Therefore, the RF signal is measured before playback operation, and
compensation is applied to bring this level to the zero level.
The difference by which the RF signal exceeds the RF AVRG value is input to the RF In register.
The value obtained by subtracting the VC AVRG value from the TE signal is input to the TRK In register.
The value obtained by subtracting the TE AVRG value from the TE signal is input to the TRK In register.
The value obtained by subtracting the VC AVRG value from the FE signal is input to the FCS In register.
The value obtained by subtracting the FE AVRG value from the FE signal is input to the FCS In register.
The value obtained by subtracting the FE AVRG value from the FE signal is input to the FZC register.
$382000 (FE Avrg. measurement on)
$380010 (TE Avrg. measurement on)
$388000 (VC Avrg. measurement on)
(Complete each AVRG measurement before starting the next.)
$38140A (RFLC, FLC0, FLC1 and TLC1 commands on)
(The required compensation should be turn on together; see Fig. 4-2.)
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CXD2548R

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