m5m4v4s40ctp-12 Mitsumi Electronics, Corp., m5m4v4s40ctp-12 Datasheet - Page 19

• Manufacturer Part Number: m5m4v4s40ctp-12
• Description: 2-bank 131072-word 16-bit Synchronous Dram
• Manufacturer: Mitsumi Electronics, Corp.

SDRAM (Rev. 0.3)
[ Read Interrupted by Precharge ]
a minimum of one CLK. A PRE command disables the data output, depending on the /CAS latency. The
figures below show examples of how the output data is terminated with a PRE command.
Feb ‘97 Preliminary
A burst read operation can be interrupted by a precharge of the same bank. The READ to PRE interval is
CL=3
CL=2
CL=1
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
Command
Command
Command
Command
Command
Command
Command
Command
CLK
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
MITSUBISHI ELECTRIC
Read Interrupted by Precharge (BL=4)
M5M4V4S40CTP-12, -15
READ
READ
READ
READ
READ
READ
READ
READ
PRE
PRE
PRE
Q0
Q0
Q0
Q0
Q0
Q1
PRE
PRE
Q0
Q0
Q0
Q1
Q1
Q2
PRE
PRE
PRE
Q1
Q1
Q2
Q2
Q3
Q2
Q2
Q3
Q3
MITSUBISHI LSIs
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