m5m4v4s40ctp-12 Mitsumi Electronics, Corp., m5m4v4s40ctp-12 Datasheet - Page 26

• Manufacturer Part Number: m5m4v4s40ctp-12
• Description: 2-bank 131072-word 16-bit Synchronous Dram
• Manufacturer: Mitsumi Electronics, Corp.

SDRAM (Rev. 0.3)
DQMU / DQML CONTROL
and DQML mask the upper and lower bytes of input, respectively. The DQMU and DQML write mask is
applied in the same clock cycle. During read operations, DQMU and DQML are used to “Hi-Z” the upper
and lower bytes of output data, respectively. The DQMU and DQML to output “Hi-Z” latency is two, i.e.,
the output will be “Hi-Z” at the rising edge of second clock after DQM is applied.
Feb ‘97 Preliminary
DQMU and DQML are used to mask write data and disable read data. During write operations, DQMU
Command
DQ(8-15)
DQ(0-7)
DQML
DQMU
CLK
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
Write
masked by DQML=High
D0
D0
masked by DQMU=High
D1
D2
MITSUBISHI ELECTRIC
D3
D3
DQMU/DQML Function
M5M4V4S40CTP-12, -15
READ
disabled by DQMU=High
Q0
Q0
disabled by DQML=High
Q1
Q2
MITSUBISHI LSIs
Q3
Q3
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