m5m4v4s40ctp-12 Mitsumi Electronics, Corp., m5m4v4s40ctp-12 Datasheet - Page 29

• Manufacturer Part Number: m5m4v4s40ctp-12
• Description: 2-bank 131072-word 16-bit Synchronous Dram
• Manufacturer: Mitsumi Electronics, Corp.

SDRAM (Rev. 0.3)
AC TIMING REQUIREMENTS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Input Pulse Levels :
Input Timing Measurement Level :
Feb ‘97 Preliminary
CLK
Signal
Symbol Parameter
tRCD
tRRD
tCLK
tRAS
tRSC
tPDE
tREF
tWR
tCH
tRC
tRP
tCL
tIS
tIH
tT
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
CLK cycle time
CLK High pulse width
CLK Low pulse width
Transition time of CLK
Input Setup time (all inputs)
Input Hold time (all inputs)
Row Cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Delay time
Mode Register Set
Cycle time
Power Down Exit time
Refresh Interval time
MITSUBISHI ELECTRIC
0.8V to 2.0V
1.4V
M5M4V4S40CTP-12, -15
CL=1
CL=2
CL=3
Min.
100
30
15
12
30
70
30
12
24
24
12
4
4
1
3
1
-12
10000
Max.
16.4
10
1.4V
1.4V
Limits
Min.
120
1.5
30
15
15
30
75
40
15
30
30
15
4
4
1
3
Any AC timing is
referenced to the input
signal passing through
1.4V.
-15
10000
Max.
16.4
10
MITSUBISHI LSIs
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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