ST72321AR STMICROELECTRONICS [STMicroelectronics], ST72321AR Datasheet - Page 156

• Manufacturer Part Number: ST72321AR
• Description: 64/44-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC,FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72321
12.8 I/O PORT PIN CHARACTERISTICS
12.8.1 General Characteristics
Subject to general operating conditions for V
Figure 81. Connecting Unused I/O Pins
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the V
tion. A positive injection is induced by V
on page 139
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see
characteristics, not tested in production.
5. The R
scribed in
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
156/189
ΣI
I
Symbol
INJ(PIN)
t
t
INJ(PIN)
t
f(IO)out
r(IO)out
w(IT)in
V
R
C
V
V
I
I
hys
PU
S
IH
L
IO
IL
3)
PU
3)
Figure
pull-up equivalent resistor is based on a resistive transistor (corresponding I
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
Injected Current on PC6 (Flash de-
vices only)
Injected Current on an I/O pin
Total injected current (sum of all I/O
and control pins)
Input leakage current
Static current consumption
Weak pull-up equivalent resistor
I/O pin capacitance
Output high to low level fall time
Output low to high level rise time
External interrupt pulse time
for more details.
82).
V
DD
10kΩ
Parameter
10kΩ
UNUSED I/O PORT
UNUSED I/O PORT
1)
1)
IN
ST72XXX
6)
>V
ST72XXX
DD
1)
5)
1)
2)
while a negative injection is induced by V
CMOS ports
V
V
Floating input mode
V
C
Between 10% and 90%
IN
DD
DD
SS
IN
L
=50pF
=
maximum must be respected, otherwise refer to I
≤
=5V
, f
V
V
SS
OSC
IN
Conditions
Figure
≤
V
, and T
DD
Figure 82. Typical I
V
81). Data based on design simulation and/or technology
DD
=5V
A
4)
unless otherwise specified.
90
80
70
60
50
40
30
20
10
0
2
0.7xV
2.5
Min
50
0
1
Ta=140°C
Ta=95°C
Ta=25°C
Ta=-45°C
DD
3
PU
3.5
IN
vs. V
PU
<V
V dd(V)
Typ
120
0.7
25
25
5
4
SS
current characteristics de-
DD
. Refer to
4.5
with V
0.3xV
5
Max
± 25
200
250
± 4
INJ(PIN)
+4
±1
5.5
section 12.2.2
DD
IN
=V
specifica-
6
SS
Unit
t
mA
CPU
µA
kΩ
pF
ns
V