bt865a Conexant Systems, Inc., bt865a Datasheet - Page 11

• Manufacturer Part Number: bt865a
• Description: Ycrcb To Ntsc/pal Digital Video Encoder
• Manufacturer: Conexant Systems, Inc.

1.1
Table 1-1.
100138C
02/17/03
CLK
RESET*
BLANK*
VSYNC*
HSYNC*
P[7:0]
Y[7:0]
TTXDAT
TTXREQ
ALTADDR
SLAVE
RGBOUT
Pin Name
1
Pin Assignments (1 of 2)
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
I
Pin Descriptions
43
47
48
49
50
35–28
25, 24, 21–16 Y pixel inputs (TTL compatible) in 16-bit YCrCb mode. Y[7] enables internal color bars when
27
38
26
42
14
Circuit Description
Pin names, input/output assignments, numbers, and descriptions are listed in
Table
details the block diagram.
Pin #
1-1.
Figure 1-1
2x pixel clock input (TTL compatible).
Reset control input (TTL compatible). A logical zero disables and resets video timing
(horizontal, vertical, subcarrier counters to the start of VSYNC of first field) and resets
the I2C interface (but does not reset I2C registers). RESET* must be a logical one for
normal operation.
Composite blanking control input (TTL compatible). BLANK* is registered on the rising
edge of CLK. The P[7:0] and Y[7:0] inputs are ignored while BLANK* is a logical zero.
Vertical sync input/output (TTL compatible). As an output (master mode operation),
VSYNC* is output following the rising edge of CLK. As an input (slave mode operation),
VSYNC* is registered on the rising edge of CLK.
Horizontal sync input/output (TTL compatible). As an output (master mode operation),
HSYNC* is output following the rising edge of CLK. As an input (slave mode operation),
HSYNC* is registered on the rising edge of CLK.
YCrCb pixel inputs (TTL compatible) in 8-bit YCrCb mode. CrCb pixel inputs (TTL
compatible) in 16-bit YCrCb mode. A higher index corresponds to a greater bit significance.
operating in 8-bit YCrCb mode. A higher index corresponds to a greater bit significance.
Teletext bit stream input (TTL compatible).
Teletext request output (TTL compatible).
Alternate slave address input (TTL compatible). A logical one configures the device to
respond to an I2C address of 0x88; a logical zero configures the device to respond to an
I2C address of 0x8A.
Slave/master mode select input (TTL compatible). A logical one configures the device for
slave video timing operation. A logical zero configures the device for master video timing
operation. This pin may be connected directly to VDD or GND.
Analog RGB control input (TTL compatible). A logical one configures the device to
output analog RGB (RGBOUT mode) and one composite video output. A logical zero
configures the device to generate S-video along with two composite video outputs. This
pin may be connected directly to VDD or GND. The RGBOUT pin is logically ORed with
the RGBO register bit.
illustrates the Bt864A/Bt865A pinout diagram, and
Conexant
(1)
Description
(1)
Figure 1-2
(1)
1-1