bt865a Conexant Systems, Inc., bt865a Datasheet - Page 49

• Manufacturer Part Number: bt865a
• Description: Ycrcb To Ntsc/pal Digital Video Encoder
• Manufacturer: Conexant Systems, Inc.

Table 2-1. Read-Back Bit Map
2.1
2.2
2.3
100138C
02/17/03
GENERAL NOTE:
ESTATUS
0
1
2
The ID[2:0] bits indicate the part number: 4 is returned from the Bt864A; 5 is returned from the Bt865A. The
version number is indicated by bits VERSION[4:0]. For this revision, VERSION[4:0] = 0x11. The CCSTAT[2] bit is
high if closed-caption data has been written for the even field; it is low immediately after the clock run-in on line
284 or 335. The CCSTAT[1] bit is high if closed-caption data has been written for the odd field; it is low
immediately after the clock run-in on line 21 or 22. The FIELD[2:0] bits represent the field number, where 000
indicates the first field.
7
Essential Registers
Important Registers
Writing Addresses
Internal Registers
A read-back bit map is given in
Bit descriptions and detailed programming information follow the bit map. When a
read does occur, only the data from
start condition if pin ALTADDR is low and 0x89 if pin ALTADDR is high. All
registers are write-only and are set to zero following a software reset. A software reset
is always performed at power-up; after power-up, a reset can be triggered by writing
the SRESET register bit.
communications.
The power-up state is defined to be black burst CCIR601 NTSC video. To enable
active video, the EACTIVE register bit must be set.
The default video format is interlaced 8-bit CCIR601 NTSC. Other video formats can
be enabled only by programming the four following registers: 0x53, 00x65, 0x66, and
0x67. Other registers may need to be programmed to get the desired timing of the
synchronization pins; these include HSYNCF[9:0] and HSYNCR[9:0].
Following a start condition, writing to slave address 0x8A initiates access to register
addresses. Alternative slave address 0x88 must be written if the ALTADDR pin is
high.
ID[2:0]
ID[2:0]
6
5
Conexant
Figure 3-5
CCSTAT[2]
4
Table
Table 2-1
illustrates timing required for I
2-1, and a register bit map is given in
CCSTAT[1]
3
can be read. To read, write 0x8B after a
VERSION[4:0]
2
FIELD[2:0]
1
2
C
Table
0
2-2.
2-1