bt865a Conexant Systems, Inc., bt865a Datasheet - Page 27

• Manufacturer Part Number: bt865a
• Description: Ycrcb To Ntsc/pal Digital Video Encoder
• Manufacturer: Conexant Systems, Inc.

Bt864A/Bt865A Data Sheet
1.5.3
1.5.4
100138C
02/17/03
Slave Mode
Master Mode
Horizontal sync (HSYNC*) and vertical sync (VSYNC*) are generated from internal
timing and from optional software bits. HSYNC* and VSYNC* are output following
the rising edge of CLK.
The HSYNC* output may be configured to have standard video timing (4.7 µs wide,
asserted at start of a line default after RESET cycle) or it may be programmed to specify
the start of HSYNC* (10-bit value) and the end of HSYNC* (10-bit value). VSYNC* is
asserted for 3 scan lines for 262/525 line formats and 2.5 scan lines for 312/625 line
formats (except for PAL-N which is 3 scan lines). When HSYNC* is configured for
standard video timing, coincident falling edges of HSYNC* and VSYNC* indicate the
beginning of the first field (CCIR convention). Auto mode detection is not applicable
under master mode operation.
The horizontal counter is incremented on every other rising edge of CLK. A falling
edge of HSYNC* resets it to one, indicating the start of a new line.
The vertical counter is incremented on the falling edge of HSYNC*. A falling edge of
VSYNC* resets it to one, indicating the start of a new field (interlaced operation) or
frame (noninterlaced operation).
A falling edge of VSYNC* that occurs within ±1/4 of a scan line from the falling edge
of HSYNC* indicates the beginning of FIELD 1. A falling edge of VSYNC* that
occurs within ±1/4 scan line from the center of the line indicates the beginning of
FIELD 2. Referring to
HSYNC* at the beginning of the next expected FIELD 1 and halfway between
expected falling HSYNC* edges at the beginning of the next expected FIELD 2.
HSYNC* and VSYNC* must remain low for at least 2 CLK cycles. The operating
mode (NTSC/PAL, interlaced/noninterlaced, square pixel/CCIR601, and setup) is
automatically determined when configured as a slave when the SETMODE bit is zero.
525-line operation is assumed, unless 625-line operation is detected by the number of
lines in a field. Interlaced operation is detected by observing the sequence of FIELD 1
or FIELD 2; if the field timing (odd follows odd, even follows even) is repeated, then
noninterlaced mode is assumed. The frequency of operation (square pixels or CCIR)
is detected by counting the number of clocks per line. The pixel rate is assumed to be
13.5 MHz unless the exact horizontal count for square pixels, ±1 count, is detected in
between two successive falling edges of HSYNC*.
By setting SETMODE = 1, the video format control register bits (VIDFORM [3:0],
SETUPDIS, NONINTL, and SQUARE) will determine the operating mode.
NOTE:
Square pixel 625-line operation with this sequence requires one frame to
stabilize.
Figure 1-4
Conexant
through , start of VSYNC* occurs on the falling
Circuit Description
1-17