bt865a Conexant Systems, Inc., bt865a Datasheet - Page 17

• Manufacturer Part Number: bt865a
• Description: Ycrcb To Ntsc/pal Digital Video Encoder
• Manufacturer: Conexant Systems, Inc.

Bt864A/Bt865A Data Sheet
Figure 1-3. HSYNC* Timing in Master Mode
1.4.2
100138C
02/17/03
GENERAL NOTE: Waveforms not to scale.
FOOTNOTE:
(1)
(2)
(3)
(4)
Horizontal Reset
Video Waveform
Analog Output
Clock/Counter
One clock delay (1/2 pixel) of HSYNC* FALLING EDGE, using register SYNCDLY.
Falling edge of HSYNC* is definable in variable HSYNC* timing mode, using the register HSYNCF.
Rising edge of HSYNC* is definable in variable HSYNC* timing mode, using the register HSYNCR.
Maximum horizontal resolution (see Table 1-2).
Internal Pixel
HSYNC*
Internal
Slave Mode
Reset
(1)
Slave mode does not support a variable HSYNC* timing mode. The default pipeline
delay from the HSYNC* falling edge to analog sync out falling edge is 47 clocks if
SYNCDLY = 0, and 46 clocks if SYNCDLY = 1. The default delay from the falling
edge of HSYNC* input to internal horizontal pixel counter reset is 5 clocks. In both
master and slave modes, the pixel data pipeline delay is 52 clocks.
Pixel Count
(4)
1
Horizontal Sync
Pipeline Delay
Default
2
(2)
3 . . .
(3)
Conexant
Color
Burst
Active
Video
(1)
Pixel Count
(4)
1
Default
Circuit Description
2
(2)
3 . . .
100138_004
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