mx25l6405 Macronix International Co., mx25l6405 Datasheet
mx25l6405
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mx25l6405 Summary of contents
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... Minimum 10K erase/program cycle for array • Minimum 100K erase/program cycle for additional 4Kb SOFTWARE FEATURES • Input Data Format - 1-byte Command code P/N: PM1107 MX25L6405 Macronix NBit 64M-BIT [x 1] CMOS SERIAL eLiteFlash • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected ...
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... GENERAL DESCRIPTION The MX25L6405 is a CMOS 67,108,864 bit serial TM eLiteFlash Memory, which is configured as 8,388,608 x 8 internally. The MX25L6405 features a serial peripheral interface and software protocol allowing operation on a simple 3- wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO) ...
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... BLOCK DIAGRAM Address Generator SI CS#, ACC, WP#,HOLD# SCLK P/N: PM1107 Memory Array Data Register Y-Decoder SRAM Buffer Mode State HV Logic Machine Generator Clock Generator 3 MX25L6405 Output Sense Buffer Amplifier SO REV.1.3, NOV. 06, 2006 ...
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... DATA PROTECTION The MX25L6405 are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences ...
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... Upper 64th (two sectors: 126 and 127) Upper 32nd (four sectors: 124 to 127) Upper sixteenth (eight sectors: 120 to 127) Upper eigthth (sixteen sectors: 112 to 127) Upper quarter (thirty-two sectors 127) Upper half (thirty-two sectors 127) All 5 MX25L6405 REV.1.3, NOV. 06, 2006 ...
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... AND PROGRAM PERFORMACE". Figure 2. ACCELERATED PROGRAM TIMING DIAGRAM V HH 12V ACC t VHH Note: tVHH (VHH Rise and Fall Time) min. 250ns P/N: PM1107 MX25L6405 Hold Hold Condition Condition (standard) (non-standard VHH ...
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... Deep Down) sector) sector) Power-down) B9 Hex A5 Hex B5 Hex AB Hex Enter Exit the the additional additional 4Kb 4Kb sector sector 7 MX25L6405 READ Fast Read Parallel Mode data) 03 Hex 0B Hex 55 Hex AD1 AD1 AD2 AD2 AD3 AD3 x n bytes Enter and ...
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... MX25L6405 Address Range 570000h 57FFFFh 560000h 56FFFFh 550000h 55FFFFh 540000h 54FFFFh 530000h 53FFFFh 520000h 52FFFFh 510000h 51FFFFh 500000h 50FFFFh 4F0000h 4FFFFFh 4E0000h 4EFFFFh 4D0000h 4DFFFFh 4C0000h 4CFFFFh 4B0000h ...
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... MX25L6405 Address Range 060000h 06FFFFh 050000h 05FFFFh 040000h 04FFFFh 030000h 03FFFFh 020000h 02FFFFh 010000h 01FFFFh 000000h 00FFFFh REV.1.3, NOV. 06, 2006 ...
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... CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is supported. P/N: PM1107 shift in MSB 10 MX25L6405 shift out MSB REV.1.3, NOV. 06, 2006 ...
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... The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte followings: 17(hex) for MX25L6405. The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data out on SO -> ...
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... Register Write erase protected Protect error block 1= status register write 1=error (note 1) disable Note: 1. see the table "Protected Area Sizes" P/N: PM1107 MX25L6405 bit 4 bit 3 bit 2 BP2 BP1 BP0 protected protected protected block block block (note 1) ...
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... When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0 software protected mode (SPM) P/N: PM1107 MX25L6405 WP# and SRWD bit status WP#=1 and SRWD bit=0, or ...
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... For normal write command (by SI), No effect c. Under parallel mode, the fastest access clock freq. will be changed to 1.5MHz(SCLK pin clock freq.) d. For parallel mode, the tAA will be change to 50ns. P/N: PM1107 TM Memory will be in parallel mode until VCC power-off. 14 MX25L6405 TM REV.1.3, NOV. 06, 2006 ...
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... Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. P/N: PM1107 MX25L6405 15 REV.1.3, NOV. 06, 2006 ...
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... RDID instruction. Even in Deep power-down mode, the RDP, RES, and REMS are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. The sequence is shown as Figure 23,24,25. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if P/N: PM1107 MX25L6405 16 REV.1.3, NOV. 06, 2006 ...
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... Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table of ID Definitions: 1. RDID: manufacturer ID MX25L6405 2. RES: MX25L6405 3. REMS: MX25L6405 P/N: PM1107 memory type C2 20 device ID 16 manufacturer MX25L6405 memory density 17 device ID 16 REV.1.3, NOV. 06, 2006 ...
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... At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress. P/N: PM1107 MX25L6405 18 REV.1.3, NOV. 06, 2006 ...
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... During voltage transitions, all pins may overshoot to -0.5V to 4.6V 4.6V or -0.5V for period up to 20ns. 4. All input and output pins may overshoot to VCC+0.5V -0.5V to 4.6V while VCC+0.5V is smaller than or equal to 4.6V. Figure 5. Maximum Positive Overshoot Waveform 4.6V 3.6V MIN. TYP 19 MX25L6405 20ns MAX. UNIT CONDITIONS 10 pF VIN = VOUT = 0V REV.1.3, NOV. 06, 2006 ...
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... Input timing referance level 0.8VCC 0.2VCC Figure 7. OUTPUT LOADING DEVICE UNDER TEST P/N: PM1107 Output timing referance level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and fall time are <5ns 2.7K ohm CL 6.2K ohm DIODES=IN3064 OR EQUIVALENT CL=30pF Including jig capacitance 20 MX25L6405 0.5VCC +3.3V REV.1.3, NOV. 06, 2006 ...
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... VCC+0.4 0.4 VCC-0.2 21 MX25L6405 TEST CONDITIONS uA VCC = VCC Max VIN = VCC or GND uA VCC = VCC Max VIN = VCC or GND uA VIN = VCC or GND CS# = VCC uA VIN = VCC or GND CS# = VCC mA f=50MHz (serial) mA f=1.5MHz (parallel) mA f=20MHz (serial) mA f=1.2MHz (parallel) ...
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... Only applicable as a constraint for a WRSR instruction when SRWD is set Test condition is shown as Figure 3. P/N: PM1107 for Commercial grade, VCC = 2.7V ~ 3.6V) Serial Serial Parallel Serial Parallel Serial Parallel Serial Parallel Serial Parallel SRWD, BP3, BP2, BP1, BP0 WIP, WEL 22 MX25L6405 Min. Typ. Max. Unit D.C. 50 MHz 1.5 MHz D.C. 20 MHz 1.2 MHz 9 ns 180 ...
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... Write Inhibit Voltage Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1107 MX25L6405 Min. Max 1.5 ...
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... Figure 8. Serial Input Timing CS# tCHSL SCLK tDVCH SI High-Z SO Figure 9. Output Timing CS# SCLK tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1107 tSLCH tCHSH tCHDX tCLCH MSB LSB tCH tCLQV tCL tQLQH tQHQL 24 MX25L6405 tSHSL tSHCH tCHCL tSHQZ LSB REV.1.3, NOV. 06, 2006 ...
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... HOLD "don't care" during HOLD operation. Figure 11. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 WP# tWHSL CS SCLK SI High-Z SO P/N: PM1107 tHLCH tCHHL tCHHH tHLQZ MX25L6405 tHHCH tHHQX tSHWL REV.1.3, NOV. 06, 2006 ...
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... P/N: PM1107 Command 06 High Command 04 High Manufacturer Identification MSB MSB 26 MX25L6405 Device Identification REV.1.3, NOV. 06, 2006 ...
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... Register MSB High 24-Bit Address MSB X 7 MSB 27 MX25L6405 Status Register Out Data Out 1 Data Out ...
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... BIT ADDRESS DATA OUT MSB MSB 28 MX25L6405 DATA OUT MSB REV.1.3, NOV. 06, 2006 ...
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... MSB Command 24 Bit Address MSB 29 MX25L6405 Data Byte Data Byte 256 MSB REV.1.3, NOV. 06, 2006 ...
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... DP Command B9 Stand-by Mode Dummy Bytes MSB Electronic Signature Out MSB Deep Power-down Mode 30 MX25L6405 Deep Power-down Mode Sequence t RES2 Stand-by Mode REV.1.3, NOV. 06, 2006 ...
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... Dummy Bytes Manufacturer MSB MSB 31 MX25L6405 Stand-by Mode 47 Device MSB REV.1.3, NOV. 06, 2006 ...
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... Figure 26. Power-up Timing (max) Program, Erase and Write Commands are Ignored V CC (min) Reset State of the Flash V WI P/N: PM1107 Chip Selection is Not Allowed tVSL Read Command is tPUW 32 MX25L6405 Device is fully allowed accessible time REV.1.3, NOV. 06, 2006 ...
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... Note 1: Chip erase and WRSR will not be executed in 4kbit mode Note 2: Chip erase can't erase this 4kbit About the fail status: Bit6 of the status register is used to state fail status, bit6=1 means program or erase have been failed. Any new write command will clear this bit. P/N: PM1107 MX25L6405 ...
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... To read array in parallel mode requires a parallel mode command (55H) before the read command. Once in the parallel mode, eLiteFlash 8. In READ mode, RES mode and REMS mode, MXIC IC will enable output an entire cycle in advance compare with other compatible vendor's spec. P/N: PM1107 TM Memory will not exit parallel mode until power-off. 34 MX25L6405 REV.1.3, NOV. 06, 2006 ...
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... Under parallel mode, the fastest access clock freq. will be changed to 1.2MHz(SCLK pin clock freq.). 7. To program in parallel mode requires a parallel mode command (55H) before the program command. Once in the parallel mode, eLiteFlash P/N: PM1107 TM Memory will not exit parallel mode until power-off. 35 MX25L6405 REV.1.3, NOV. 06, 2006 ...
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... In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will enable output half a cycle in advance compare with other compatible vendor's spec. P/N: PM1107 Manufacturer Identification High-Z X Byte output Device Identification TM Memory will not exit parallel mode until power-off. 36 MX25L6405 REV.1.3, NOV. 06, 2006 ...
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... P/N: PM1107 Dummy Bytes Electronic Signature Out X Byte Output Deep Power-down Mode TM Memory will not exit parallel mode until power-off. 37 MX25L6405 RES2 Stand-by Mode REV.1.3, NOV. 06, 2006 ...
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... In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will enable output half a cycle in advance compare with other compatible vendor's spec. P/N: PM1107 TM Memory will not exit parallel mode until power-off. 38 MX25L6405 REV.1.3, NOV. 06, 2006 ...
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... P/N: PM1107 Dummy Bytes ADD ( Manufacturer ID X Device ID TM Memory will not exit parallel mode until power-off. 39 MX25L6405 47 REV.1.3, NOV. 06, 2006 ...
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... For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1107 tSLCH tDVCH tCHDX MSB IN High Impedance Figure A. AC Timing at Device Power-Up Notes 1 40 MX25L6405 tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN Min. Max. Unit 0.5 500000 us/V REV ...
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... Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1107 Min. TYP. (1) Max. (2) UNIT 128 256 s 102 180 0.8 2 2.4 9.6 mS 10K cycles 100K cycles 41 MX25L6405 Comments Note (4) Note (4) Note (4) Note (4) Note (4) Excludes system level overhead(3) MIN. MAX. -1.0V 12.5V -1.0V 2 VCCmax -1.0V VCC + 1.0V -100mA +100mA REV.1.3, NOV. 06, 2006 ...
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... ORDERING INFORMATION PART NO. ACCESS TIME(ns) MX25L6405MC-20 20 MX25L6405MC-20G 20 MX25L6405MI-20 20 MX25L6405MI-20G 20 P/N: PM1107 OPERATING STANDBY Temperature PACKAGE CURRENT(mA) CURRENT(uA MX25L6405 Remark 0~70 C 16-SOP 0~70 C 16-SOP Pb-free -40~85 C 16-SOP -40~85 C 16-SOP Pb-free REV.1.3, NOV. 06, 2006 ...
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... PART NAME DESCRIPTION 6405 P/N: PM1107 MX25L6405 OPTION: G: Pb-free blank: normal SPEED: 20: 50MHz, for SPI TEMPERATURE RANGE: C: Commercial (0˚C to 70˚C) I: Industrial (-40˚C to 85˚C) PACKAGE: M: 300mil 16-SOP DENSITY & MODE: 6405: 64Mb TYPE DEVICE: 25: Serial Flash 43 REV.1.3, NOV. 06, 2006 ...
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... PACKAGE INFORMATION P/N: PM1107 MX25L6405 44 REV.1.3, NOV. 06, 2006 ...
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... Removed "Preliminary" title 2. Added "Recommended Operating Conditions" 3. Added "additional 4Kb erase time" and "cycle time" 4. Added "Part Name Description" separated from MX25L1605, MX25L3205, MX25L6405 to MX25L6405 1.1 1. Improved chip erase time: without ACC=12V : 160s(typ.)/512s(max.)-->128s(typ.)/256s(max.) with ACC=12V : 128s(typ.)/410s(max.)-->102s(typ.)/180s(max.) 2 ...
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... Macronix's products in the prohibited applications ACRONIX NTERNATIONAL Headquarters Macronix America, Inc. Macronix Japan Cayman Islands Ltd. Macronix (Hong Kong) Co., Limited. http : //www.macronix.com C L O., TD. Taipei Office Macronix Europe N.V. Singapore Office MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 46 MX25L6405 ...