mx25l512c Macronix International Co., mx25l512c Datasheet
mx25l512c
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mx25l512c Summary of contents
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... Status Register Feature • Electronic Identification - JEDEC 2-byte Device ID - RES command, 1-byte Device ID HARDWARE FEATURES • SCLK Input - Serial clock input P/N: PM1469 MX25L512C 512K-BIT [x 1] CMOS SERIAL FLASH 1 REV. 1.0, APR. 14, 2009 ...
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... All Pb-free devices are RoHS Compliant GENERAL DESCRIPTION MX25L512C is a CMOS 524,288 bit serial Flash memory, which is configured as 65,536 x 8 internally. MX25L512C features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input ...
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... SCLK 6 GND 8-PIN TSSOP (173mil) 1 CS# VCC HOLD# 7 WP# 3 SCLK 6 4 GND 5 SI P/N: PM1469 MX25L512C 8-LAND USON (2x3mm) CS# 1 VCC 8 2 HOLD WP# 3 SCLK GND 5 PIN DESCRIPTION SYMBOL DESCRIPTION CS# Chip Select SI Serial Data Input SO Serial Data Output ...
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... BLOCK DIAGRAM Address Generator Data SI Register Mode CS# Logic SCLK Clock Generator P/N: PM1469 Memory Array Page Buffer Y-Decoder SRAM Buffer Sense Amplifier State HV Machine Generator 4 MX25L512C Output Buffer SO REV. 1.0, APR. 14, 2009 ...
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... DATA PROTECTION MX25L512C is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state ma- chine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences ...
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... To re-start communication with chip, the HOLD# must be at high and CS# must be at low. P/N: PM1469 Protect level BP0 0 0 (none (All (All (All) Hold Condition (standard) (non-standard) 6 MX25L512C 512b None All All All Hold Condition REV. 1.0, APR. 14, 2009 ...
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... DP(Deep (Release CE (Chip PP(Page Power from Deep Erase) Program) Down (hex) B9 (hex) AB (hex) (hex) AD1 AD2 AD3 7 MX25L512C WRSR Fast Read READ (fast read (read data) register) data) 01 (hex) 03 (hex) 0B (hex) AD1 AD1 AD2 AD2 AD3 AD3 x n bytes read ...
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... CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1469 00FFFFh : 003FFFh 002FFFh 001FFFh 000FFFh shift in MSB 8 MX25L512C shift out MSB REV. 1.0, APR. 14, 2009 ...
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... RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manu- facturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte followings: 10(hex) for MX25L512C. The sequence of issuing RDID instruction is: CS# goes low→sending RDID instruction code→24-bits ID data out on SO→ ...
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... Note: 1. See the table "Protected Area Sizes". 2. The endurance cycles of protect bits are 100,000 cycles; however, the tW time out spec of protect bits is relaxed 15ms ( multiple of 10,000 cycles, ex for 20,000 cycles) after 10,000 cycles on those bits. P/N: PM1469 MX25L512C bit4 bit3 bit2 BP1 ...
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... When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0 software protected mode (SPM) P/N: PM1469 MX25L512C WP# and SRWD bit status WP#=1 and SRWD bit=0, or ...
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... Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI → CS# goes high. (see Figure 19) P/N: PM1469 MX25L512C 12 REV. 1.0, APR. 14, 2009 ...
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... If less than 256 bytes are sent to the device, the data is programmed at the request address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ P/N: PM1469 MX25L512C 13 REV. 1.0, APR. 14, 2009 ...
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... Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power Down Mode. P/N: PM1469 MX25L512C 14 REV. 1.0, APR. 14, 2009 ...
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... Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table of ID Definitions: manufacturer ID RDID Command RES Command manufacturer ID REMS Command P/N: PM1469 memory type C2 20 electronic ID 05 device MX25L512C memory density 10 REV. 1.0, APR. 14, 2009 ...
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... The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the figure of "power-up timing". Note stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend- ed.(generally around 0.1uF) P/N: PM1469 MX25L512C 16 REV. 1.0, APR. 14, 2009 ...
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... All input and output pins may overshoot to VCC+0.5V while VCC+0.5V is smaller than or equal to 4.6V. Figure 3.Maximum Negative Overshoot Waveform 20ns 0V -0.5V CAPACITANCE TA = 25° 1.0 MHz SYMBOL PARAMETER CIN Input Capacitance COUT Output Capacitance P/N: PM1469 MX25L512C Industrial grade Figure 4. Maximum Positive Overshoot Waveform 4.6V 3.6V MIN. TYP MAX. UNIT ...
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... Figure 6. OUTPUT LOADING DEVICE UNDER TEST P/N: PM1469 Output timing referance level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and fall time are <5ns 2.7K ohm CL 6.2K ohm DIODES=IN3064 OR EQUIVALENT CL=30pF Including jig capacitance (CL=15pF Including jig capacitance for 70MHz) 18 MX25L512C 0.5VCC +3.3V REV. 1.0, APR. 14, 2009 ...
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... VCC+0.4 0.4 VCC-0.2 19 MX25L512C UNITS TEST CONDITIONS VCC = VCC Max uA VIN = VCC or GND VCC = VCC Max uA VIN = VCC or GND VIN = VCC or GND uA CS#=VCC VIN = VCC or GND uA CS#=VCC f=85MHz mA SCLK=0.1VCC/0.9VCC, SO=Open f=66MHz mA SCLK=0 ...
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... Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set Test condition is shown as Figure 3. P/N: PM1469 MX25L512C Min. Typ. (Condition:15pF) 1KHz (Condition:30pF) 1KHz ...
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... Note: 1. The parameter is characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1469 Parameter Min MX25L512C Max. Unit us REV. 1.0, APR. 14, 2009 ...
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... Figure 7. Serial Input Timing CS# tCHSL SCLK tDVCH SI SO Figure 8. Output Timing CS# SCLK tCLQV tCLQX SO ADDR.LSB IN SI P/N: PM1469 tSLCH tCHSH tCHDX tCLCH MSB High-Z tCH tCLQV 22 MX25L512C tSHSL tSHCH tCHCL LSB tCL tSHQZ LSB tQLQH tQHQL REV. 1.0, APR. 14, 2009 ...
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... HOLD "don't care" during HOLD operation. Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 WP# tWHSL CS SCLK SI High-Z SO P/N: PM1469 tHLCH tCHHL tCHHH tHLQZ MX25L512C tHHCH tHHQX tSHWL REV. 1.0, APR. 14, 2009 ...
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... SI 9F High-Z SO P/N: PM1469 Command 06 High Command 04 High Manufacturer Identification MSB MSB 24 MX25L512C Device Identification REV. 1.0, APR. 14, 2009 ...
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... Status Register MSB High 24-Bit Address MSB 7 MSB 25 MX25L512C Status Register Out Data Out 1 Data Out ...
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... P/N: PM1469 BIT ADDRESS DATA OUT MSB MSB 26 MX25L512C DATA OUT MSB REV. 1.0, APR. 14, 2009 ...
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... Address MSB MSB Data Byte MSB 27 MX25L512C Data Byte Data Byte 256 MSB REV. 1.0, APR. 14, 2009 ...
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... Figure 20. Block Erase (BE) Sequence (Command 52 or D8) CS# SCLK SI Note: BE command D8(hex). P/N: PM1469 Bit Address Command MSB Command 24 Bit Address MSB 28 MX25L512C REV. 1.0, APR. 14, 2009 ...
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... DP Command B9 Stand-by Mode Dummy Bytes MSB Electronic Signature Out MSB Deep Power-down Mode 29 MX25L512C Deep Power-down Mode RES2 Stand-by Mode REV. 1.0, APR. 14, 2009 ...
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... Dummy Bytes Manufacturer MSB MSB 30 MX25L512C Stand-by Mode 47 Device MSB REV. 1.0, APR. 14, 2009 ...
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... Figure 26. Power-up Timing (max) Chip Selection is Not Allowed V CC (min) P/N: PM1469 MX25L512C tVSL Device is fully accessible 31 time REV. 1.0, APR. 14, 2009 ...
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... For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1469 tSLCH tDVCH tCHDX MSB IN High Impedance Figure A. AC Timing at Device Power-Up Notes 1 32 MX25L512C tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN Min. Max. Unit 0.5 500000 us/V REV ...
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... Input Voltage with respect to GND on ACC Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1469 MX25L512C Min. TYP. (1) Max. ( ...
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... ORDERING INFORMATION CLOCK PART NO. (MHz) CURRENT MAX. (mA) MX25L512CMI-12G 85 MX25L512CZUI-12G 85 MX25L512COI-12G Advanced Information P/N: PM1469 OPERATING STANDBY CURRENT MAX. (uA MX25L512C Temperature PACKAGE Remark 8-SOP -40~85°C Pb-free (150mil) 8-USON -40~85°C Pb-free (2x3mm) 8-TSSOP -40~85°C Pb-free (173mil) REV. 1.0, APR. 14, 2009 ...
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... PART NAME DESCRIPTION 512C P/N: PM1469 MX25L512C OPTION: G: Pb-free SPEED: 12: 85MHz TEMPERATURE RANGE: I: Industrial (-40°C to 85°C) PACKAGE: M: 150mil 8-SOP ZU: 2x3mm 8-USON O: 173mil 8-TSSOP DENSITY & MODE: 512C: 512Kb TYPE DEVICE: 25: Serial Flash 35 REV. 1.0, APR. 14, 2009 ...
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... PACKAGE INFORMATION P/N: PM1469 MX25L512C 36 REV. 1.0, APR. 14, 2009 ...
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... P/N: PM1469 MX25L512C 37 REV. 1.0, APR. 14, 2009 ...
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... P/N: PM1469 MX25L512C 38 REV. 1.0, APR. 14, 2009 ...
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... REVISION HISTORY Revision No. Description 1.0 1. Removed "Low Vcc write inhibit" function 2. Modified max sector erase time from 120ms to 260ms 3. Modified tCH & tCL timing 4. Removed "Advanced Information" P/N: PM1469 MX25L512C Page P5,16,21,31 P1,20,33 P20 P1 39 Date APR/13/2009 REV. 1.0, APR. 14, 2009 ...
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... Macronix Europe N.V. Koningin Astridlaan 59, Bus 1 1780 Wemmel Belgium Tel: +32-2-456-8020 Fax: +32-2-456-8021 Macronix Offices : USA Macronix America, Inc. 680 North McCarthy Blvd. Milpitas, CA 95035, U.S.A. Tel: +1-408-262-8887 Fax: +1-408-262-8810 MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 40 MX25L512C ...