sed1355 ETC-unknow, sed1355 Datasheet - Page 409
sed1355
Manufacturer Part Number
sed1355
Description
Sed1355 Embedded Ramdac Lcd/crt Controller
Manufacturer
ETC-unknow
Datasheet
1.SED1355.pdf
(509 pages)
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Epson Research and Development
Vancouver Design Center
4 PC Card to SED1355 Interface
4.1 Hardware Description
Interfacing to the PC Card Bus
Issue Date: 99/05/05
The SED1355 is designed to directly support a variety of CPUs, providing an interface to
each processor’s unique “local bus”. However, in order to provide support for processors
not having an appropriate local bus, the SED1355 supports a specific PC Card interface.
The SED1355 provides a “glueless” interface to the PC Card bus except for the following.
• The RESET# signal on the SED1355 is active low and must be inverted to support the
• Although the SED1355 supports an asynchronous bus interface, a clock source is
In this implementation, the address inputs (AB[20:0]) and data bus (DB[15:0]) connect
directly to the CPU address (A[20:0]) and data bus (D[15:0]). M/R# is treated as an address
line so that it can be controlled using system address A21.
The PC Card interface does not provide a bus clock, so one must be supplied for the
SED1355. Since the bus clock frequency is not critical, nor does it have to be synchronous
to the bus signals, it may be the same as CLKI. BS# (bus start) is not used and should be
tied high (connected to V
active high RESET provided by the PC Card interface.
required on the BUSCLK input pin.
DD
).
X23A-G-005-05
SED1355
Page 13
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