sed1355 ETC-unknow, sed1355 Datasheet - Page 486
sed1355
Manufacturer Part Number
sed1355
Description
Sed1355 Embedded Ramdac Lcd/crt Controller
Manufacturer
ETC-unknow
Datasheet
1.SED1355.pdf
(509 pages)
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Page 12
4 V
4.1 Hardware Description
SED1355
X23A-G-011-03
R
4121 to SED1355 Interface
NEC V
ADD[25:0]
R
DAT[15:0]
LCDRDY
BUSCLK
4121
LCDCS#
SHB#
V
V
WR#
RD#
DD
DD
Note:
When connecting the SED1355 RESET# pin, the system designer should be aware of all
conditions that may reset the SED1355 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Note
The NEC V
controller. It provides all the necessary internal address decoding and control signals
required by the SED1355.
The diagram below shows a typical implementation utilizing the SED1355.
3
2
Figure 4-1: NEC V
For pin mapping see Table 3-1:, “Host Bus Interface Pin Mapping,” on page 10.
+3.3V
+2.5V
R
4121 microprocessor is specifically designed to support an external LCD
ADD21
R
4121 to SED1355 Configuration Schematic
System RESET
Pull-up
Interfacing to the NEC VR4121™ Microprocessor
V
DD
(+3.3V)
Epson Research and Development
SED1355
WE0#
WE1#
RD#
CS#
WAIT#
M/R#
AB[20:0]
DB[15:0]
BUSCLK
BS#
RD/WR#
V
RESET#
DD
Vancouver Design Center
Issue Date: 99/05/05
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