sed1355 ETC-unknow, sed1355 Datasheet - Page 501

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
2.1.2 Access Cycles
Interfacing to the NEC V832™ Microprocessor
Issue Date: 99/05/05
SDCLKOUT
LLBEN,
LUBEN
READY
A[23:1]
D[15:0]
D[15:0]
(write)
IORD,
IOWR
(read)
CSn
Once an address in the appropriate range is placed on the external address bus (A[23:1]),
the corresponding chip select (CSn) is driven low. The read or write enable signals (IORD
or IOWR) are driven low and READY is driven low by the SED1355 to insert wait states
into the cycle. The byte enable signals (LLBEN and LUBEN) allow byte steering.
The following figure illustrates typical NEC V832 memory-mapped IO access cycles.
Figure 2-1: NEC V832 Read/Write Cycles
Hi-Z
VALID
VALID
VALID
X23A-G-012-01
SED1355
Hi-Z
Page 9