sed1355 ETC-unknow, sed1355 Datasheet - Page 48
sed1355
Manufacturer Part Number
sed1355
Description
Sed1355 Embedded Ramdac Lcd/crt Controller
Manufacturer
ETC-unknow
Datasheet
1.SED1355.pdf
(509 pages)
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SED1355
X23A-A-001-11
Symbol
t11
t10
t12
t13
t14
t15
t16
t9
t1
t2
t3
t4
t5
t6
t7
t8
2
1
Clock period
Clock pulse width high
Clock pulse width low
A[20:0], M/R#, RD/WR# setup to CKIO
A[20:0], M/R#, RD/WR# hold from CS#
BS# setup
BS# hold
CSn# setup
Falling edge RD# to D[15:0] driven
Rising edge CSn# to RDY# tri-state
Falling edge CSn# to RDY# driven
CKIO to WAIT# delay
D[15:0] setup to 2
D[15:0] hold (write cycle)
D[15:0] valid to RDY# falling edge (read cycle)
Rising edge RD# to D[15:0] tri-state (read cycle)
Note
1.
2.
The SH-4 Wait State Control Register for the area in which the SED1355 resides must be set to a
non-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value (with ref-
erence to BUSCLK).
If the SED1355 host interface is disabled, the timing for RDY# driven is relative to the falling
edge of CSn# or the first positive edge of CKIO after A[20:0], M/R# becomes valid,
whichever one is later.
If the SED1355 host interface is disabled, the timing for D[15:0] driven is relative to the falling
edge of RD# or the first positive edge of CKIO after A[20:0], M/R# becomes valid,
whichever one is later.
nd
CKIO after BS# (write cycle)
a
b
Two Software WAIT States Required
One Software WAIT State Required
Parameter
Table 7-1: SH-4 Timing
Min
15
10
6
6
3
0
4
1
4
0
5
0
4
0
0
5
3.0V
a
Max
25
15
20
25
Epson Research and Development
Hardware Functional Specification
Min
2.5
3.6
2.5
15
10
6
6
3
0
4
1
4
0
0
0
0
Vancouver Design Center
5.0V
Issue Date: 99/05/18
b
Max
10
10
12
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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