lxt6155 Intel Corporation, lxt6155 Datasheet - Page 15

• Manufacturer Part Number: lxt6155
• Description: 155 Mbps Sdh/sonet/atm Transceiver
• Manufacturer: Intel Corporation

2.2.1.2
2.2.2
Datasheet
then performs clock recovery operation, comparing the reshaped data phase against the receive
output clock phase. The receive PLL requires an external reference (e.g. transmit input clock or
XTAL clock) to start up the clock recovery process. This clock can be derived from XTALIN,
TPICLK or TSICLK ( 8). The recovered clock is used to retime the CMI signals, and to decode
CMI to NRZ. Coding errors are detected and flagged via the CMIERR pin in HW mode with the
frame detect disabled or in serial mode. In software mode (HWSEL = High) CMI coding errors are
indicated via the P interface interrupt register: Reg #15, mode 05.
NRZ Mode
The on chip adaptive equalizer is bypassed. Data goes straight to the clock recovery phase locked
loop. The PLL then performs clock recovery operation, comparing the data phase against the clock
phase. This clock can be derived from XTALIN, TPICLK or TSICLK ( 8). The receive PLL
requires an external reference (e.g. transmit input clock or XTAL clock) to start up the clock
recovery process.
The recovered clock is used to retime the data signals. When the recovered clock is within 488 ppm
of the reference clock, the LOCK signal asserts. This alarm is also accessible on the P interface as
a status bit (Reg #15, mode 0) and as an interrupt (Reg #15, mode 05). Once the recovered clock
has been obtained and the NRZ data has been recovered, the LXT6155 performs frame-detect-and-
byte-alignment, and serial-to-parallel conversion. The LXT6155 optionally provides output data
RPOD<7:0> aligned to the SDH/SONET byte boundary. The user has the option to enable/disable
the frame-alignment function in both hardware and software mode. The frame detect/byte
alignment function generates the receive output frame pulse (ROFP). In HW mode (HWSEL =
Low) ROFP asserts (high) on the third A2 byte. In SW mode (HWSEL = High) this position is
programmable via register #13, bits <6:3>. When byte alignment is disabled and the LXT6155 is in
CMI mode, the ROFP pin indicates CMI coding errors including polarity errors for ones and
inversion errors for zeroes.
The clock recovery PLL’s center frequency comes from either the local crystal or a stable transmit
input clock (TSICLKP/TSICLKN or TPICLK). If operated in loop-timed mode or remote loopback
mode, an external reference clock must be used to center the internal PLL clock. In remote
loopback, the receive reference remains either XTALIN or TSICLK or TPICLK, depending on the
control selection. If an independent and stable transmit clock is available, the designer has the
option of applying this clock to pin XTALIN to center the PLL, without the external crystal.
The user can also replace the crystal by connecting the TPICLK (19.44MHz) signal to the XTALIN
pin. However, a local crystal is recommended for “keep alive” purposes in case the clock becomes
unavailable.
Receive Frame Detect and Byte Alignment
Receive Frame Detection only operates in parallel mode, if Frame Detection is enabled. The
LXT6155 provides aligned bytes RPOD<7:0> following the distinct SONET OC3/STM1 frame
marker word, 3 x A1, followed by 3 x A2, where A1=F6h and A2=28h. The Receive Output Frame
Pulse (ROFP) asserts during the third A2 byte, and de-asserts after one complete RPOCLK clock
period. If this feature is used, it can be enabled in register #12 bit <3> in software mode
setting the RIFE (pin 15) high in hardware mode prior to applying data to Rtip/Rring. Two
consecutive frames with correct frame words (A
of-frame state (OOF) to an in-frame state. The OOF alarm is accessible in SW mode (HWSEL =
High) as a status or interrupt signal (Reg #15). To declare an OOF condition, four consecutive
1. For further details see register #12 description for usage.
155 Mbps SDH/SONET/ATM Transceiver — LXT6155
1
...A
1
A
2
...A
2
) are required to change from an out-
1
, or by
15