lxt6155 Intel Corporation, lxt6155 Datasheet - Page 29

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lxt6155

Manufacturer Part Number
lxt6155
Description
155 Mbps Sdh/sonet/atm Transceiver
Manufacturer
Intel Corporation
Datasheet

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Datasheet
1. This register is used in CMI (co-ax) mode only.
Bit
3:2
Bit
7:5
4:3
2:1
Bit
7:4
Bit
7:5
4:3
1
0
0
3
2
1
0
2
1
0
Table 13. Equalizer & AGC, Register #5 (Address A<3:0>=0101) (Continued)
Table 14. Matching Filter 2, Register #6 (Address A<3:0>=0110)
Table 15. Slicer, Register #7 (Address A<3:0>=0111)
Table 16. RxPLL 1, Register #8 (Address A<3:0>=1000)
Default
Default
Default
Default
0.0.0.0
0.1.0
0.1.1
0.0
1.0
0.0
0.0
1
0
1
1
0
0
0
0
0
1
agc_adapt_gain
Mnemonic
Mnemonic
Mnemonic
Mnemonic
afe_ena
-
AGC adaption step size:
00 = 1
01 = 2
10 = 4
11 = 8
Analog front end enable (also enables matching filter oscillator core):
0 = disabled (no bias)
1 = enabled
Not for customer use
Not for customer use
Not for customer use
Not for customer use
Not for customer use
Unused
Not for customer use
Not for customer use
Not for customer use
Not for customer use
Not for customer use
Not for customer use
Unused
Not for customer use
155 Mbps SDH/SONET/ATM Transceiver — LXT6155
Description
Description
Description
Description
29

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