k4j55323qf-gc Samsung Semiconductor, Inc., k4j55323qf-gc Datasheet - Page 12

• Manufacturer Part Number: k4j55323qf-gc
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4J55323QF-GC
CAS LATENCY (READ LATENCY)
data. The latency can be set to 5~9 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will
be available nominally coincident with clock edge n+m. Below table indicates the operating frequencies at which each CAS latency set-
ting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
COMMAND
COMMAND
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output
RDQS
RDQS
/CK
CK
/CK
CK
DQ
DQ
Burst Length = 4 in the cases shown
Shown with nominal t
SPEED
-12
-14
-16
-20
READ
READ
T0
T0
≤
≤
CL=9
AC
700
800
-
-
and nominal t
DON’T CARE
CAS Latency
NOP
NOP
T4
T3
≤
CL=8
DSDQ
600
-
-
-
Allowable operating
- 12 -
CL = 6
CL = 5
Frequency (MHz)
TRANSITIONING DATA
CL=7
≤
500
-
-
-
NOP
NOP
T5
T4
CL=6
-
-
-
-
256M GDDR3 SDRAM
NOP
T6
NOP
T5
CL=5
-
-
-
-
Rev 1.7 (Jan. 2005)
T6n
T5n