k4j55323qf-gc Samsung Semiconductor, Inc., k4j55323qf-gc Datasheet - Page 4

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k4j55323qf-gc

Manufacturer Part Number
k4j55323qf-gc
Description
256mbit Gddr3 Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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2M x 32Bit x 4 Banks Graphic Double Data Rate 3 Synchronous DRAM
with Uni-directional Data Strobe
FEATURES
GENERAL DESCRIPTION
FOR 2M x 32Bit x 4 Bank GDDR3 SDRAM
• 2.0V + 0.1V power supply for device operation
• 2.0V + 0.1V power supply for I/O interface
• On-Die Termination (ODT)
• Output Driver Strength adjustment by EMRS
• Calibrated output drive
• Pseudo Open drain compatible inputs/outputs
• 4 internal banks for concurrent operation
• Differential clock inputs (CK and CK)
• Commands entered on each positive CK edge
• CAS latency : 5, 6, 7, 8 and 9 (clock)
• Additive latency (AL): 0 and 1 (clock)
• Programmable Burst length : 4
• Programmable Write latency : 1, 2, 3, 4, 5 and 6 (clock)
• Single ended READ strobe (RDQS) per byte
• Single ended WRITE strobe (WDQS) per byte
The 8Mx32 GDDR3 is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words
by 32 bits, fabricated with SAMSUNG
extremely high performance up to 5.6GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, and programmable latencies allow the device to be useful for a variety of high performance memory
system applications.
K4J55323QF-GC
ORDERING INFORMATION
*K4J55323QF-GL20/VL20 : VDD & VDDQ = 1.8V+0.1V(1.7V ~ 1.9V)
*K4J55323QF-V is the Lead Free package part number
K4J55323QF-GC20*
K4J55323QF-GC14
K4J55323QF-GC15
K4J55323QF-GC16
Part NO.
’s
high performance CMOS technology. Synchronous features with Data Strobe allow
Max Freq.
700MHz
667MHz
600MHz
500MHz
- 4 -
• RDQS edge-aligned with data for READs
• WDQS center-aligned with data for WRITEs
• Data Mask(DM) for masking WRITE data
• Auto & Self refresh mode
• Auto Precharge option
• 32ms, auto refresh (4K cycle)
• 144 Ball FBGA
• Maximum clock frequency up to700MHz
• Maximum data rate up to 1.4Gbps/pin
• DLL for outputs
Max Data Rate
1400Mbps/pin
1334Mbps/pin
1200Mbps/pin
1000Mbps/pin
Open Drain
Interface
Pseudo
256M GDDR3 SDRAM
Rev 1.7 (Jan. 2005)
144 - Ball FBGA
Package

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