k4j55323qf-gc Samsung Semiconductor, Inc., k4j55323qf-gc Datasheet - Page 45

• Manufacturer Part Number: k4j55323qf-gc
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Recommended operating conditions (
K4J55323QF-GC
CLOCK INPUT OPERATING CONDITIONS
Note : 1. This provides a minimum of 1.16V to a maximum of 1.36V, and is always 70% of VDDQ
Note : 1 . Outputs measured into equivalent load of 10pf at a driver impedance of 40
Clock Input Mid-Point Voltage ; CK and /CK
Clock Input Voltage Level; CK and /CK
Clock Input Differential Voltage ; CK and /CK
Clock Input Differential Voltage ; CK and /CK
Clock Input Crossing Point Voltage ; CK and /CK
2. For AC operations, all DC clock requirements must be satisfied as well.
3. The value of VIX is expected to equal 70% VDDQ for the transmitting device and must track variations in the DC level of the same.
4. VID is the magnitude of the difference between the input level in CK and the input level on /CK.
5. The CK and /CK input reference level (for timing referenced to CK and /CK) is the point at which CK and /CK cross;
6. CK and /CK input slew rate must be > 3V/ns
the input reference level for signals other than CK and /CK is VREF.
Parameter/ Condition
GDDR3
0°C ≤ Tc ≤85°C ; VDD=2.0V + 0.1V, VDDQ=2.0V + 0.1V
V
REF
ZQ
Output Load Circuit
240
Symbol
V
V
V
V
V
Ω
MP(DC)
IN(DC)
ID(DC)
ID(AC)
IX(AC)
1.26V
- 45 -
Z
0
=60
V
Ω
Ω
REF
.
1.16
0.42
0.22
0.22
Min
- 0.15
V
DDQ
10pf
60
256M GDDR3 SDRAM
Ω
)
V
V
V
V
REF
DDQ
DDQ
DDQ
Max
1.36
+ 0.15
Rev 1.7 (Jan. 2005)
+ 0.3
+ 0.5
+ 0.3
Unit Note
V
V
V
V
V
1,2,3
2,4
2
4
3